Prosecution Insights
Last updated: July 17, 2026
Application No. 18/474,887

METHOD AND APPARATUS FOR DETECTING CLUSTERS OF WAFER DEFECTS

Non-Final OA §103§112
Filed
Sep 26, 2023
Priority
Oct 18, 2022 — RE 10-2022-0134473 +1 more
Examiner
NGUYEN, HUNG
Art Unit
2853
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Electronics Co., Ltd.
OA Round
1 (Non-Final)
91%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 91% — above average
91%
Career Allowance Rate
1330 granted / 1466 resolved
+22.7% vs TC avg
Moderate +9% lift
Without
With
+8.9%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 2m
Avg Prosecution
30 currently pending
Career history
1498
Total Applications
across all art units

Statute-Specific Performance

§101
1.6%
-38.4% vs TC avg
§103
55.7%
+15.7% vs TC avg
§102
16.9%
-23.1% vs TC avg
§112
8.9%
-31.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1466 resolved cases

Office Action

§103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. With respect to claims 1, 12 and 18, the meaning, scope and breadth of the term “unique values” render the claims indefinite. The claims do not specify: what constitutes a “value” of a grid area (e.g., defect count, height data, statistical metric, identifier, etc.) nor what renders such values “unique”. As to claims 1, 2, 7, 8, 9, 10, 11, 12, 14-20 recite: “obtaining a plurality of target grid areas...using unique values”. However, no objective criteria or algorithm is provided for selecting “target grid areas” from the grid areas and the term depends on the undefined concept of “unique values”. As to claim 10, it is not clear what coefficients a, b and c stand for? They are not defined. Notwithstanding the above-noted indefiniteness for purposes of examination, the claims are interpreted as broadly as reasonably possible in particular: “ unique values” are interpreted to encompass any distinguishable data associated with grid areas; “target grid areas” are interpreted as any subset of grid areas selected based on such data. Under this broadest reasonable interpretation, the claimed subject matter is directed to processing wafer measurement data, dividing such data into regions, selecting regions based on data characteristics, grouping the regions and prioritizing them for analysis. As discussed below, the prior art teaches or suggests each of these features, either explicitly or inherently. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1, 2, 8, 12 and 18, are rejected under 35 U.S.C. 103 as being unpatentable over Keck et al (WO2006017155 A2) in view of Kulkarni et al (U.S Pat. 5,991,699 A1) . As to claim 1, Keck discloses an apparatus (figure 1) and a corresponding method for detecting clusters of wafer defects comprising: measuring each of a plurality of wafers to obtain a plurality of wafer level maps of a plurality of wafer measurement points ( see page 27, lines 20-25) and generating composite wafer data (86) for defect analysis (see figure 16). Keck does not expressly disclose dividing the composite wafer level map into a plurality of grid areas and grouping selected grid areas into cluster and obtaining a detection priority, as claimed. Kulkarni teaches converting defect data into a Cartesian format and diving the inspected wafer area/die into quadrangles (shown as squares in figure 4) having side length Dm, thereby teaching division of wafer-related defect information into grid areas. Kulkarni further teaches “spatial clustering” where defects are identified and collected in distinct cluster such that defects within a cluster are adjacent to at least one other defect in the same cluster, and teaches use of a critical distance to identify defect pairs likely to be close together (see inspection station 100, analysis station 102 figure 4, quadrangle with side length Dm). In view of such teachings, it would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to incorporate the teachings of Keck and Kulkarni to come up with the claimed invention. It would have been obvious to a skilled artisan to modify the composite wafer analysis of Keck with the grid-based defect partitioning and adjacent-based clustering of Kulkarni in order to identify localized defect regions within the composite wafer and to group adjacent defect related regions for improved defect pattern recognition and analysis efficiency. As to claim 2, Keck discloses outputting defects and detection data for analysis (see abstract). As to claim 8, Kulkarni discloses the grouping of the plurality of target grid areas into the plurality of target grid clusters includes grouping adjacent target grid areas of the plurality of target grid areas into a same target grid cluster of the plurality of target grid cluster (see figure 4, clustering description). As to claims 12 and 18, Keck discloses a memory (02; 04) for storing a program for detecting the wafer defects and a processor (06) configured to execute the program stored in the memory. Allowable Subject Matter Claims 3-7, 9-11, 13-17 and 19-20 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims. While the prior arts of record, disclose combining wafer data into composite wafer maps and performing spatial clustering of defect-related data. However, the prior arts fail to teach or suggest several specific limitations recited in the mentioned claims. As to claims 3 and 15, the prior arts of record do not teach or suggest obtaining wafer maps from rear surface height measurements or applying height-based thresholds to generate wafer level maps. As to claims 4-5 and 13, the prior arts do not teach or suggest: dynamically defining grid spacing based on statistical properties of measurement point distribution, nor using axis-based average intervals to determine grid resolution. As to claims 7, 14 and 19, the prior arts of record do not teach or suggest: region-specific filtering criteria based on spatial location (center vs. edge) or using different thresholds to process different wafer regions. As to claim 9 and 15, the prior arts of record disclose clustering but do not teach or suggest: post-processing clusters to adjust their size relative to the wafer-level spatial representation. As to claims 10 and 16, the prior arts of record do not disclose or suggest: the particular score function as claimed, nor combining lot-based and wafer-based metrics in the claimed manner to determine priority. As to claims 11, 17 and 20, the prior arts of record do not teach or suggest: combining spatial expansion with height-based threshold conditions or expanding clusters based on both value-based and distance-based criteria. Prior Art Made of Record The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Ypma et al (US 10,642,162); Fouquet et al (U.S.Pat. 7,904,845) and O’Dell et al (U.S.Pat. 6,826,298) disclose wafer defect inspection systems and have been cited for technical background. Any inquiry concerning this communication or earlier communications from the examiner should be directed to HUNG HENRY NGUYEN whose telephone number is (571)272-2124. The examiner can normally be reached Monday-Friday 7:00AM-4:30PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Toan Minh Ton can be reached at 571-272-2303. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. HUNG HENRY NGUYEN Primary Examiner Art Unit 2882 Hvn 4/16/26 /HUNG V NGUYEN/ Primary Examiner, Art Unit 2882
Read full office action

Prosecution Timeline

Sep 26, 2023
Application Filed
Apr 21, 2026
Non-Final Rejection mailed — §103, §112
Jun 05, 2026
Interview Requested
Jun 16, 2026
Applicant Interview (Telephonic)
Jun 16, 2026
Examiner Interview Summary

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Prosecution Projections

1-2
Expected OA Rounds
91%
Grant Probability
99%
With Interview (+8.9%)
2y 2m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1466 resolved cases by this examiner. Grant probability derived from career allowance rate.

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