DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nishiwaki et al. (U.S. Publication No. 2011/0201187).
Regarding claim 1, Nishiwaki teaches a semiconductor device, comprising:
a semiconductor substrate (Fig. 1, substrate 30) of a first conductivity type (n-type), the semiconductor substrate having a first main surface (top surface) and a second main surface (bottom surface) opposite to each other;
a first semiconductor layer 22) of a second conductivity type (p-type), provided at the first main surface of the semiconductor substrate (Fig. 1), the first semiconductor layer having a first surface (top surface) and a second surface (bottom surface) opposite to each other, the second surface facing the semiconductor substrate (Fig. 1);
a plurality of first semiconductor regions (20) of the first conductivity type (Fig. 1), selectively provided in the first semiconductor layer (Fig. 1), at the first surface of the first semiconductor layer (Fig. 1);
a plurality of trenches (trenches 35) penetrating through the plurality of first semiconductor regions and the first semiconductor layer and reaching the semiconductor substrate (Fig. 1);
a plurality of gate electrodes (electrode 36) provided in the plurality of trenches, via a plurality of gate insulating films (insulating film 37), respectively;
a first electrode (see paragraph [0044], emitter electrode not shown) provided at the first surface of the first semiconductor layer and on the plurality of first semiconductor regions (paragraph [0044]); and
a second electrode (paragraph [0044], collector electrode not shown) provided at the second main surface of the semiconductor substrate (paragraph [0044]), wherein
each of the plurality of first semiconductor regions has a surface facing the first electrode (top surface),
each of the plurality of gate electrodes has a surface facing the first electrode (top surface), and
in a depth direction of the semiconductor device, a distance between the surface of any one of the plurality of first semiconductor regions and the surface of one of the plurality of gate electrodes that is closest to said any one of the plurality of first semiconductor regions is in a range of 0.1μm to 0.3μm (see Fig. 11 and paragraph [0062], H1 is distance between top of gate electrode and top of emitter region, and is 0.3 um).
Conclusion
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/EVAN G CLINTON/ Primary Examiner, Art Unit 2899
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