Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 2/7/2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The subject matter of this application admits of illustration by a drawing to facilitate understanding of the invention. Applicant is required to furnish a drawing under 37 CFR 1.81(c). No new matter may be introduced in the required drawing. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d).
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the inner gate structures recited in claim 1, 9 , 16 and 21 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
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Claim 1, 9 , 16 and 21 objected to because of the following informalities: the claim appears to have a typographical error " wherein each of the one or more inner gate structures has a generally concave outer edge that conforms to a generally convex inner edge of an associated inner gate spacer of the one or more inner gate spacers". The inner gate structures are formed by removing and replacing sacrificial SiGe sheets 208, 210 and 212 in paragraph [0042] fig2F. The inner gate structure will have the same shape as replaced 208, 210 and 212 as shown in fig2F. For the purpose of examination, the examiner will interpret the above limitation as "wherein each of the one or more inner gate structures has a generally convex outer edge that conforms to a generally concave inner edge of an associated inner gate spacer of the one or more inner gate spacers". Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-4, 8-12, 16-17 and 21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by More et al. US 2022/0149176.
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Re claim 1, More teaches an electronic device having one or more Gate-All-Around (GAA) transistors (fig1 and 17E), at least one of the one or more GAA transistors comprising:
one or more inner gate structures (100/102, fig17E, [64, 68]) having a work function metal (work function tuning layers, [64]) bounded by a gate dielectric (100, fig17E, [64]); and
one or more inner gate spacers (90, fig17E, [68]) associated with the one or more inner gate structures (100/102, fig17E, [68]),
wherein each of the one or more inner gate structures has a generally convex outer edge that conforms to a generally concave inner edge of an associated inner gate spacer of the one or more inner gate spacers (fig17E).
Re claim 2, More teaches the electronic device of claim 1, wherein: the generally convex outer edge of each of the one or more inner gate structures comprises a generally flat region terminating at upper and lower rounded corners (center region of 100/102, fig17E).
Re claim 3, More teaches the electronic device of claim 2, wherein: the upper and lower rounded corners have a corner rounding between about 1 nanometer to 2 nanometers (thickness of 90 of 1-5nm, fig17E, [23]).
Re claim 4, More teaches the electronic device of claim 1, wherein the GAA transistor further comprises: a first stack of channel structures (54A/B, fig17E and 18A/B, [61]) extending between a source structure (92, fig17E and 18B, [68]) and a drain structure (92, fig17E and 18B, [68]) of the GAA transistor; and
wherein the one or more inner gate structures comprise a second stack of inner gate structures (100/102 of fig 17E on other side of fig 18A/B) associated with the first stack of channel structures, and the one or more inner gate spacers comprise a third stack of inner gate spacers (90 of fig 17E on other side of fig 18A/B) associated with the second stack of inner gate structures.
Re claim 8, More teaches the electronic device of claim 1, wherein the electronic device comprises at least one of: a music player; a video player; an entertainment unit; a navigation device; a communications device ([2]); a mobile device ([2]); a mobile phone ([2]); a smartphone; a personal digital assistant; a fixed location terminal; a tablet computer, a computer ([2]); a wearable device; a laptop computer; a server; an internet of things (IoT) device; or a device in an automotive vehicle.
Re claim 9, More teaches a Gate-All-Around (GAA) transistor (fig1 and 17E), comprising:
one or more inner gate structures (100/102, fig17E, [64, 68]) having a work function metal (work function tuning layers, [64]) bounded by a gate dielectric (100, fig17E, [64]); and
one or more inner gate spacers (90, fig17E, [68]) associated with the one or more inner gate structures (100/102, fig17E, [68]),
wherein each of the one or more inner gate structures has a generally convex outer edge that conforms to a generally concave inner edge of an associated inner gate spacer of the one or more inner gate spacers (fig17E).
Re claim 10, More teaches the GAA transistor of claim 9, wherein: the generally convex outer edge of each of the one or more inner gate structures comprises a generally flat region terminating at upper and lower rounded corners (center region of 100/102, fig17E).
Re claim 11, More teaches the GAA transistor of claim 10, wherein: the upper and lower rounded corners have a corner rounding between about 1 nanometer and 2 nanometers (thickness of 90 of 1-5nm, fig17E, [23]).
Re claim 12, More teaches the GAA transistor of claim 9, wherein the GAA transistor further comprises: a first stack of channel structures (54A/B, fig17E and 18A/B, [61]) extending between a source structure (92, fig17E and 18B, [68]) and a drain structure (92, fig17E and 18B, [68]) of the GAA transistor; and wherein the one or more inner gate structures comprise a second stack of inner gate structures (100/102 of fig 17E on other side of fig 18A/B) associated with the first stack of channel structures, and the one or more inner gate spacers comprise a third stack of inner gate spacers (90 of fig 17E on other side of fig 18A/B) associated with the second stack of inner gate structures.
Re claim 16, More teaches a method of forming a gate-all-around (GAA) transistor (fig1 and 17E), comprising:
forming a plurality of channel structures (54A/B, fig17E and 18A/B, [61]) between a source (92, fig17E and 18B, [68]) and a drain (92, fig17E and 18B, [68]) of the GAA transistor;
forming a plurality of inner gate structures (100/102, fig17E, [68]),
wherein each inner gate structure of the plurality of inner gate structures (100/102, fig17E, [68]) is associated with a corresponding channel structure (54A/B, fig17E and 18A/B, [61]) of the plurality of channel structures; and
forming a plurality of inner gate spacers (90, fig17E, [68]), wherein each inner gate spacer of the plurality of inner gate spacers is associated with a corresponding inner gate structure (100/102, fig17E, [68]) of the plurality of inner gate structures, and
wherein each inner gate structure is formed to have a generally convex outer edge conforming to a generally concave inner edge of a corresponding inner gate spacer (fig17E).
Re claim 17, More teaches the method of claim 16, wherein: the plurality of channel structures (54A/B, fig17E and 18A/B, [61]) is formed as a first stack of inner channel structures; plurality of inner gate structures is formed as a second stack of inner gate structures (100/102 of fig 17E on other side of fig 18A/B); and the plurality of inner gate spacers (90 of fig 17E on other side of fig 18A/B) are formed as a third stack of inner gate structures.
Re claim 21, More teaches a method of forming a gate-all-around (GAA) transistor (fig1 and 17E), comprising:
forming a multi-layer structure having alternating silicon (53 as Si, fig2B, [19]) and silicon-germanium sheets (51 as SiGe, fig2B, [19]),
wherein the silicon-germanium sheets have different interlayer layer germanium concentrations (51A-D, fig2B, [20]);
subjecting the multi-layer structure to an etching process to form etched silicon-germanium sheets (52, fig10D, [48]),
wherein the etching process employs an etchant that etches each silicon-germanium sheet at a rate corresponding to a germanium concentration of the silicon-germanium sheet (fig10D, [20, 48]);
forming inner gate spacers (90, fig17E and 11B, [68]) about the etched silicon-germanium sheets;
removing the etched silicon-germanium sheets from the multi-layer structure (98, fig16B, [61]); and
forming gate structures (100/102, fig17E, [68]) in regions of the multi-layer structure from which the etched silicon-germanium sheets were removed.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5-7, 13-15 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over More et al. US 2022/0149176 in view of Zhang et al. US 2020/0066839.
Re claim 5, More does not explicitly show the electronic device of claim 4, wherein: the second stack of inner gate structures has an outer edge profile that is substantially vertical.
Zhang teaches the second stack of inner gate structures (36, 38 and 40 of 102, fig13, [69, 70, 71, 73]) has an outer edge profile that is substantially vertical (fig13).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of More and Zhang to adjust the thickness of the gate dielectric material according to the required voltage drop. The motivation to do so is to improve integration density and design flexibility according to device application (Zhang, [3, 4]; More, [3]).
Re claim 6, More modified above teaches the electronic device of claim 5, wherein: the outer edge profile has a slope greater than 87 degrees (Zhang, 36, 38 and 40 of 102, fig13, [69, 70, 71, 73]).
Re claim 7, More modified above teaches the electronic device of claim 6, wherein: the outer edge profile has a slope of approximately 90 degrees (Zhang, 36, 38 and 40 of 102, fig13, [69, 70, 71, 73]).
Re claim 13, More does not explicitly show the GAA transistor of claim 12, wherein: the second stack of inner gate structures has an outer edge profile that is substantially vertical.
Zhang teaches the second stack of inner gate structures (36, 38 and 40 of 102, fig13, [69, 70, 71, 73]) has an outer edge profile that is substantially vertical (fig13).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of More and Zhang to adjust the thickness of the gate dielectric material according to the required voltage drop. The motivation to do so is to improve integration density and design flexibility according to device application (Zhang, [3, 4]; More, [3]).
Re claim 14, More modified above teaches the GAA transistor of claim 13, wherein: the outer edge profile has a slope greater than 87 degrees (Zhang, 36, 38 and 40 of 102, fig13, [69, 70, 71, 73]).
Re claim 15, More modified above teaches the GAA transistor of claim 14, wherein: the outer edge profile has a slope of approximately 90 degrees (Zhang, 36, 38 and 40 of 102, fig13, [69, 70, 71, 73]).
Re claim 18, More does not explicitly show the method of claim 17, wherein: the second stack of inner gate structures has an outer edge profile that is substantially vertical.
Zhang teaches the second stack of inner gate structures (36, 38 and 40 of 102, fig13, [69, 70, 71, 73]) has an outer edge profile that is substantially vertical (fig13).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of More and Zhang to adjust the thickness of the gate dielectric material according to the required voltage drop. The motivation to do so is to improve integration density and design flexibility according to device application (Zhang, [3, 4]; More, [3]).
Re claim 19, More modified above teaches the method of claim 18, wherein: the outer edge profile has a slope greater than 87 degrees (Zhang, 36, 38 and 40 of 102, fig13, [69, 70, 71, 73]).
Re claim 20, More modified above teaches the method of claim 18, wherein: the outer edge profile has a slope of approximately 90 degrees (Zhang, 36, 38 and 40 of 102, fig13, [69, 70, 71, 73]).
Claim(s) 22-27 are rejected under 35 U.S.C. 103 as being unpatentable over More et al. US 2022/0149176 in view of Wu et al. US 2023/0137528.
Re claim 22, More does not explicitly show the method of claim 21, wherein: at least one silicon-germanium sheet has an intra-layer germanium concentration that varies across a height of the at least one silicon-germanium sheet.
Wu teaches tuning etching profile of SiGe layer ([25]) with nonuniform Ge distribution along Z direction ([25]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of More and Wu to adjust the Ge concentration of the sacrificial layer as in Wu. The motivation to do so is to achieve desired etch profile (Wu, [25]) and simplify process by reducing an implantation etching tuning step.
Re claim 23, More modified above teaches the method of claim 22, wherein: the at least one silicon-germanium sheet includes: an upper region having a first germanium concentration (Wu, top CGmax, [25]), a mid-region having a second germanium concentration (Wu, middle CGmin, [25]), and a lower region having a third germanium concentration (Wu, bottom CGmax, [25]).
Re claim 24, More modified above teaches the method of claim 23, wherein: the first and third germanium concentrations have a substantially same germanium concentration (Wu, top/bottom CGmax, [25]); and the second germanium concentration is less than both the first and third germanium concentrations (Wu, middle CGmin, [25]).
Re claim 25, More modified above teaches the method of claim 23, wherein: the etched silicon-germanium sheets have a generally vertical recess profile (More, fig17D-E or 17G-H).
Re claim 26, More modified above teaches the method of claim 25, wherein: the generally vertical recess profile has a slope greater than 87 degrees (More, fig17D, or 17G).
Re claim 27, More modified above teaches the method of claim 25, wherein: the generally vertical recess profile has a slope of approximately 90 degrees (More, fig17D, or 17G).
Conclusion
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/XIAOMING LIU/Examiner, Art Unit 2812