DETAILED ACTION
Email Communication
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Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 01/07/2026 has been entered.
Response to Amendment
Applicant’s amendment of 01/07/2026 does not place the Application in condition for allowance.
Claims 12-31 are currently pending. In response to Office Action mailed on 10/07/2025, Applicant has amended claims 12, 21 and 29.
Status of the Rejections
Due to Applicant’s amendment to claims 12, 21 and 29, all rejections from the Office Action mailed on 10/07/2025 are withdrawn. However, upon further consideration, a new ground of rejection is presented below.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 12-13, 15, 17, 19-22, 24, 26 and 28-31 are rejected under 35 U.S.C. 103 as being unpatentable over Pomerene et al. (US 6,559,538 B1) in view of Tan et al. (US 2019/0295943 A1).
Regarding claims 12 and 21, Pomerene discloses a method of fabricating semiconductor device (figures 2c-2g), comprising:
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Figure 1: Semiconductor device
providing a semiconductor substrate (28, fig. 2d, 3:5-7) having a first/top surface (bottom surface) and a second/bottom surface (top surface) opposite the first/top surface (bottom surface) (3:23-27) (see annotated figure), wherein the substrate comprises an active region comprising one or more active devices (active circuitry such as transistors in the passivation layer 23, see figures 2b, 2:25-46);
providing a through-silicon via structure (N+ and P+ regions, figs. 2e-2f, 3:7-34) extending completely through the semiconductor substrate (28) from the first surface to the second surface (see figs. 2e-2f; see also annotated figure below), the through-silicon via structure comprising a first through-silicon via (N+ region) containing a first conductivity type material (n-type) and a second through-silicon via (P+ region) containing a second conductivity type material (p-type) opposite the first conductivity type material (n-type) (figs. 2e-2f, 3:7-34) and
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Figure 2: Semiconductor Device
providing a first conductive layer (conductive layer 27, fig. 2c, 2-65-66) on the first/top surface (bottom surface) of the semiconductor substrate (28) and comprising a first portion (middle portion) coupled to a first end (bottom end) of the first through-silicon via (N+ region) and a first end (bottom end) of the second through-silicon via (P+ region) (see figure 2f).
Pomerene further discloses the semiconductor device is an integrated circuit device (see Abstract). Pomerene further discloses that the semiconductor substrate (28) is a lead telluride substrate (3:5-7). However, Pomerene does not explicitly disclose that the semiconductor substrate is a silicon substrate.
Tan is directed to an integrated circuit device (see Title, [0002], and [0045]), which a semiconductor device, wherein substrate (101) is a silicon substrate, which can be bulk silicon or SOI ([0045]). Tan, in an alternative, discloses that the substrate can be a lead telluride substrate ([0045]). Thus, Tan explicitly discloses that the Si substrate and PbTe substrate can be substituted one for the other to form the substrate of an integrated circuit device.
The Supreme Court in KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007) identified that “simple substitution of one known element for another to obtain predictable results” is obvious (See MPEP §2143).
Therefore, it would have been obvious to one skilled in the art at the time of the invention to have used the Si substrate as taught by Tan to form the substrate of Pomerene because “simple substitution of one known element for another to obtain predictable results” is obvious (See MPEP §2143).
Regarding claims 13 and 22, Pomerene as modified further discloses providing a second conductive layer (conductive layer 31, fig. 2f and 3:35-45) on the second/bottom surface (top surface) of the silicon substrate (28) and comprising a first portion (portion that is connected to middle N+ region) coupled to a second end (top end) of the first through-silicon via (N+ region) and a second portion (portion that is connected to middle P+ region) coupled to a second end (top end) of the second through-silicon via (P+ region), the first and second portions of the second conductive layer (38) being electrically isolated from each other (the conductive layer 31 is patterned to have isolated portions) (figure 2f and 3:35-38).
Regarding claims 15 and 24, Pomerene further discloses the through-silicon via structure further comprises: a third through-silicon via (N+ region) containing the first conductivity type material (n-type) and having a first end (bottom end) and a second end (top end) opposite the first end; a fourth through-silicon via (P+ region) containing the second conductivity type material (p-type) and having a first end (bottom end) and a second end (top end) opposite the first end (see figure 2f that shows plurality of N+ and P+ regions); the first conductive layer (27) comprising a second portion (right portion, see fig. 2f) coupled to the first end (bottom end) of the third through-silicon via (N+ regions) and the first end (bottom end) of the fourth through-silicon via (P+ regions); and the second portion (right portion) of the second conductive layer (31) coupled to the second end (top end) of the third through-silicon via (N+ region) (see fig. 2f).
Regarding claims 17 and 26, Pomerene further discloses providing a conformal liner (formed by substrate 28) on sidewalls of the through-silicon via structure (see fig. 2f).
Regarding claim 19, Pomerene as modified by Tan further discloses that the substrate isa bulk silicon substrate (see [0045] of Tan).
Regarding claims 20 and 28, there is no structural or material difference between the semiconductor device of Pomerene as modified (see fig. 2g) and that of the instant claim. Thus, a voltage across the first through-silicon via and the second through-silicon via must be a function of a temperature difference between the first surface of the substrate and the second surface of the silicon substrate, as in the case of the instant application.
Regarding claim 29, Pomerene discloses a method of fabricating semiconductor device (figures 2c-2g), comprising:
providing a semiconductor substrate (28, fig. 2d, 3:5-7) having a top surface (bottom surface) and a bottom surface (top surface) opposite each other (3:23-27) (see annotated figure 1), wherein the substrate comprises an active region comprising one or more active devices (active circuitry such as transistors in the passivation layer 23, see figures 2b, 2:25-46);
providing a first through-silicon via (N+ region) completely extending through the semiconductor substrate (28) from the top surface to the bottom surface (figs. 2e-2f, 3:7-34) (see annotated fig. 2), the first through-silicon via containing a first conductivity type material (n-type) (figs. 2e-2f, 3:7-34) and
providing a second through-silicon via (P+ region) extending through the semiconductor substrate (28) (figs. 2e-2f, 3:7-34), the second through-silicon via containing a second conductivity type material (p-type) opposite the first conductivity type material (n-type) (figs. 2e-2f, 3:7-34) and
providing a first conductive layer (conductive layer 27, fig. 2c, 2-65-66) on the top surface (bottom surface) of the semiconductor substrate (28) and comprising a first portion (middle portion) coupled to a first end (bottom end) of the first through-silicon via (N+ region) and a first end (bottom end) of the second through-silicon via (P+ region) (see figure 2f).
Pomerene further discloses the semiconductor device is an integrated circuit device (see Abstract). Pomerene further discloses that the semiconductor substrate (28) is a lead telluride substrate (3:5-7). However, Pomerene does not explicitly disclose that the semiconductor substrate is a silicon substrate.
Tan is directed to an integrated circuit device (see Title, [0002], and [0045]), which a semiconductor device, wherein substrate (101) is a silicon substrate, which can be bulk silicon or SOI ([0045]). Tan, in an alternative, discloses that the substrate can be a lead telluride substrate ([0045]). Thus, Tan explicitly discloses that the Si substrate and PbTe substrate can be substituted one for the other to form the substrate of an integrated circuit device.
The Supreme Court in KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007) identified that “simple substitution of one known element for another to obtain predictable results” is obvious (See MPEP §2143).
Therefore, it would have been obvious to one skilled in the art at the time of the invention to have used the Si substrate as taught by Tan to form the substrate of Pomerene because “simple substitution of one known element for another to obtain predictable results” is obvious (See MPEP §2143).
Pomerene as modified further discloses the silicon substrate comprises an active region comprising one or more active devices (active circuitry such as transistors in the passivation layer 23, see figures 2b, 2:25-46).
Regarding claim 30, Pomerene as modified further discloses providing a second conductive layer (conductive layer 31, fig. 2f and 3:35-45) on the bottom surface (top surface) of the silicon substrate (28) and comprising a first portion (portion that is connected to middle N+ region) coupled to a second end (top end) of the first through-silicon via (N+ region) and a second portion (portion that is connected to middle P+ region) coupled to a second end (top end) of the second through-silicon via (P+ region), the first and second portions of the second conductive layer (38) being electrically isolated from each other (the conductive layer 31 is patterned to have isolated portions) (figure 2f and 3:35-38).
Regarding claim 31, Pomerene further discloses providing a third through-silicon via (N+ region) containing the first conductivity type material (n-type) and having a first end (bottom end) and a second end (top end) opposite the first end; and providing a fourth through-silicon via (P+ region) containing the second conductivity type material (p-type) and having a first end (bottom end) and a second end (top end) opposite the first end (see figure 2f that shows plurality of N+ and P+ regions); wherein the first conductive layer (27) comprising a second portion (right portion, see fig. 2f) coupled to the first end (bottom end) of the third through-silicon via (N+ regions) and the first end (bottom end) of the fourth through-silicon via (P+ regions); and the second portion (right portion) of the second conductive layer (31) coupled to the second end (top end) of the third through-silicon via (N+ region) (see fig. 2f).
Claims 14 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Pomerene et al. (US 6,559,538 B1) in view of Tan et al. (US 2019/0295943 A1) as applied above, and further in view of Tan et al. (US 2015/0179543 A1).
Regarding claims 14 and 23, Pomerene is silent as to providing a first solder bump coupled to the first portion of the second conductive layer; and providing a second solder bump coupled to the second portion of the second conductive layer.
Tan discloses a method of making semiconductor device wherein solder bumps used as means to connect p-type and n-type regions to the conductive layers ([0022]).
Therefore, it would have been obvious to one skilled in the art at the time of the invention to have used the solder bumps as taught by Tan to connect the p-type and n-type regions of Pomerene with the conductive layers, as shown by Tan and also desired by Pomerene.
Claims 16 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Pomerene et al. (US 6,559,538 B1) in view of Tan et al. (US 2019/0295943 A1) as applied above, and further in view of Boukai et al. (US 2018/0351069 A1).
Regarding claims 16 and 25, Pomerene is silent as to providing a metal silicide layer having a first silicide portion disposed on an upper surface of the first through-silicon via, and a second silicide portion disposed on an upper surface of the second through-silicon via.
Boukai discloses a metal silicide layer is formed on the semiconductor regions to reduce the contact resistance between metal contact and other layers ([0200]).
Therefore, it would have been obvious to one skilled in the art at the time of the invention to have used the metal silicide layer as taught by Boukai on the upper surfaces of the semiconductor regions of Pomerene to reduce the contact resistance, as shown by Boukai.
Claims 18 and 27 are rejected under 35 U.S.C. 103 as being unpatentable over Pomerene et al. (US 6,559,538 B1) in view of Tan et al. (US 2019/0295943 A1) as applied above, and further in view of Nagakubo et al. (US 5,515,682).
Regarding claims 18 and 27, Pomerene is silent as to providing a detection circuit configured to determine an electrical signal that is a function of a temperature difference between the first and second surfaces of the semiconductor substrate.
Nagakubo discloses a method of making a Peltier device, similar to Pomerene, that comprises a detection circuit (Peltier control circuit that detects temperature, abstract) configured to determine an electrical signal that is a function of a temperature difference between first and second surfaces of a substrate (Abstract and claim 1).
Therefore, it would have been obvious to one skilled in the art at the time of the invention to have used the Peltier control circuit as taught by Nagakubo in the method of Pomerene such that the temperature of the device can detected, as shown by Nagakubo.
Response to Arguments
Applicant's arguments with respect to claims 12-31 have been considered but are moot in view of the new ground(s) of rejection as necessitated by the amendments.
Applicant argues that Pomerene does not disclose that the substrate comprises an active region comprising one or more active devices.
The examiner respectfully disagrees. Pomerene discloses that the substrate comprises an active region comprising one or more active devices (active circuitry such as transistors in the passivation layer 23, see figures 2b, 2:25-46).
Correspondence/Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GOLAM MOWLA whose telephone number is (571)270-5268. The examiner can normally be reached on M-Th, 7am - 4pm.
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/GOLAM MOWLA/Primary Examiner, Art Unit 1721