Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 11 – 12, 15, 16, 18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nakazawa (US 20200051942).
Regarding claim 11, Nakazawa discloses a high-frequency module, comprising:
a module substrate (substrate of module 1 or substrate 90, Fig. 3A) including a first major surface (top surface, Fig. 3A) and a second major surface (bottom surface) that are opposite to each other;
a plurality of electronic circuitry disposed on the first major surface (circuitry on top surface of the substrate 90), on the second major surface, and within the module substrate; and
a plurality of external connection terminals (terminal 93 on the bottom surface of the module 90) disposed on the second major surface,
wherein the plurality of electronic circuitry include:
a first electronic circuitry including a first filter (filter 61T) coupled to a power amplifier (power amplifier 11);
a second electronic circuitry including a second filter (filter 62R) coupled to a low-noise amplifier (low-noise amplifier 21); and
a third electronic circuitry including the low-noise amplifier (low noise amplifier 22),
the first electronic circuitry is disposed one of on the first major surface (top surface of the substrate), on the second major surface, or within the module substrate,
the second electronic circuitry is disposed one of on the first major surface (top surface of the substrate), on the second major surface, and within the module substrate, and
the third electronic circuitry is disposed one of on the first major surface (top surface of the substrate), on the second major surface, and within the module substrate.
Regarding claim 12, Nakazawa discloses the claimed invention as set forth in claim 11. Nakazawa suggests the first electronic circuitry is disposed on the first major surface (top surface).
Regarding claim 15, Nakazawa discloses the claimed invention as set forth in claim 11. Nakazawa further suggests a first ground electrode pattern (ground wiring 110b, outer electrode 104c, shield 10) within the module substrate, wherein the first ground electrode pattern is disposed between the first electronic circuitry and the second electronic circuitry (the grounding is disposed in many places in the circuitry. It is understandable that the ground may be positioning between the circuitries).
Regarding claim 16, Nakazawa discloses the claimed invention as set forth in claim 11. Nakazawa further suggests a second ground electrode pattern (ground wiring 110b, outer electrode 104c, shield 10) within the module substrate, wherein the second ground electrode pattern is disposed between the second electronic circuitry and the third electronic circuitry (the grounding is disposed in many places in the circuitry. It is understandable that the ground may be positioning between the circuitries).
Regarding claim 18, Nakazawa discloses the claimed invention as set forth in claim 11. Nakazawa further suggests the first filter has a pass band (paragraph 47) including an uplink operation band of a frequency division duplex (duplex 61 - 63) band, and the second filter has a pass band (paragraph 47) including a downlink operation band of the FDD band (uplink and downlink are the signal conducting nature of the circuitry).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nakazawa (US 20200051942), in view of Saji (US 20150119102).
Regarding claim 13, Nakazawa discloses the claimed invention as set forth in claim 11.
Nakazawa does not explicitly disclose the second electronic circuitry is disposed within the module substrate.
Saji suggests the components may be buried inside a substrate (Fig. 4).
It would have been obvious to one having skill in the art at the effective filing date of the invention to place the component in both surface and inside the substrate in order to fit all components in the limited space of the substrate.
Claim(s) 14, 19, 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nakazawa (US 20200051942), in view of Murase (US 20190267339).
Regarding claim 14, Nakazawa discloses the claimed invention as set forth in claim 11.
Nakazawa does not explicitly disclose the third electronic circuitry is disposed on the second major surface.
Murase teaches the components may be disposed on both surfaces of the substrate.
It would have been obvious to one having skill in the art at the effective filing date of the invention
Regarding claim 19, Nakazawa discloses the claimed invention as set forth in claim 11.
Nakazawa does not explicitly disclose the plurality of electronic circuitry include a fourth electronic circuitry including a third filter coupled to the power amplifier and the low-noise amplifier, and the fourth electronic circuitry is disposed on the first major surface.
Murase suggests a filter (22, Fig. 2) coupled to a power amplifier 31 and low-noise amplifier (33).
It would have been obvious to one having skill in the art at the effective filing date of the invention to rearrange the component as needed to form an intended circuitry.
Regarding claim 20, Nakazawa, in view of Murase, discloses the claimed invention as set forth in claim 19. Nakazawa further suggests the third electronic circuitry includes a switch (switch 54, Fig. 1) coupled between the second filter and the low-noise amplifier and between the third filter and the low-noise amplifier.
Allowable Subject Matter
Claims 1 – 10 are allowed.
Claim 17 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Reasons for Allowance
The following is an examiner’s statement of reasons for allowance:
Regarding claim 1, the prior art of record, taken alone or in combination, fails to teach or fairly suggest, in combining with other limitations recited in claim 1, a combination of limitations that a second module substrate including a third major surface and a fourth major surface that are opposite to each other, the third major surface being disposed facing the second major surface; a plurality of electronic circuitry disposed between the second major surface and the third major surface, on the first major surface, and on the fourth major surface; and a plurality of external connection terminals disposed on the fourth major surface, wherein the plurality of electronic components include: a first electronic circuitry including a first filter coupled to a power amplifier; a second electronic circuitry including a second filter coupled to a low-noise amplifier; and a third electronic circuitry including the low-noise amplifier , the first electronic circuitry is disposed one of between the second major surface and the third major surface, on the first major surface, or on the fourth major surface, the second electronic circuitry is disposed one of between the second major surface and the third major surface, on the first major surface, or on the fourth major surface, and the third electronic circuitry is disposed one of between the second major surface and the third major surface, on the first major surface, or on the fourth major surface. None of the reference art of record discloses or renders obvious such a combination.
Regarding claim 17, the prior art of record, taken alone or in combination, fails to teach or fairly suggest, in combining with other limitations recited in claim 11, a combination of limitations that the third electronic circuitry includes a low-noise amplifier (LNA) controller controlling the low-noise amplifier. None of the reference art of record discloses or renders obvious such a combination.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Aramata (US 20180167094) discloses a filter and power amplifier circuitry, Fig. 1
Murata (US 20160006408) discloses a filter and power amplifier circuitry, Fig. 1
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BINH B TRAN whose telephone number is (571)272-9289. The examiner can normally be reached M-F 8:00 AM - 6:00 PM.
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/BINH B TRAN/Primary Examiner, Art Unit 2848