DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 4-5, 8, 11-12, and 14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cho et al. (US PG-Pub No.: 2022/0246533 A1, hereinafter, “Cho”).
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Regarding claim 1, Cho discloses an electronic package, comprising:
a substrate (10, FIG. 1) having a first region (annotated FIG. 1 above) and a second region (annotated FIG. 1 above);
a first set of electronic components (11b, FIG. 1) mounted on the substrate (10) in the first region;
a second set of electronic components (11a+11b, FIG. 1) mounted on the substrate (10) in the second region;
an encapsulant layer (13, FIG. 1) disposed on the substrate (10) and encapsulating the first and second sets of electronic components (11a+11b);
a set of interconnect components (12, FIG. 1) disposed on the substrate (10) in the second region, and extending through the encapsulant layer (13), wherein the set of interconnect components (12) are electrically coupled to the first and second sets of electronic components (11a+11b, ¶ [0024]); and
a connector (14, FIG. 1) mounted on the encapsulant layer (13) and electrically coupled to the first and second sets of electronic components (11a+11b) through the set of interconnect components (12, FIG. 1).
Regarding claim 2, Cho discloses the electronic package of claim 1, wherein a portion of the encapsulant layer (13) in the first region is thicker than another portion of the encapsulant layer (13) in the second region (as shown in FIG. 1, both first region and second region have different thickness).
Regarding claim 4, Cho discloses the electronic package of claim 1, wherein the set of interconnect components (12) are solder balls or conductive pillars (FIG. 1).
Regarding claim 5, Cho discloses the electronic package of claim 1, wherein the connector (14) is a board-to-board connector (FIG. 1).
Regarding claim 8, Cho discloses a method for making an electronic package (see Cho, FIG. 1), the method comprising:
providing a substrate (10, FIG. 1) having a first region (annotated FIG. 1 above) and a second region (annotated FIG. 1 above);
mounting a first set of electronic components (11b, FIG. 1) on the substrate (10) in the first region;
mounting a second set of electronic components (11a+11b, FIG. 1) on the substrate (10) in the second region;
mounting a set of interconnect components (12, FIG. 1) on the substrate (10) in the second region;
forming an encapsulant layer (13, FIG. 1) on the substrate (10) to encapsulate the first and second sets of electronic components (11a+11b) and the set of interconnect components (12, FIG. 1);
forming a set of openings through the encapsulant layer (13) to expose the set of interconnect components (12); and
mounting a connector (14, FIG. 1) on the interconnect components (12), wherein the connector (14) has a set of terminals (14s+14c, FIG. 1) that are aligned with the set of openings respectively, such that the connector (14) is electrically coupled to the first and second sets of electronic components (11a+11b) through the set of interconnect components (12, FIG. 1).
Regarding claim 11, Cho discloses the method of claim 8, wherein before mounting the connector (14) on the encapsulant layer (13), the method further comprises: filling within the set of openings respective conductive fillers to elevate the set of interconnect components (12) to substantially above the encapsulant layer (13, FIGs. 4D and 4E).
Regarding claim 12, Cho discloses the method of claim 8, wherein a portion of the encapsulant layer (13) in the first region is thicker than another portion of the encapsulant layer (13) in the second region (FIG. 1; thickness of both regions varies).
Regarding claim 14, Cho discloses the method of claim 8, wherein the set of interconnect components (12) are solder balls or conductive pillars (FIG. 1).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 3 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Cho et al. (US PG-Pub No.: 2022/0246533 A1, hereinafter, “Cho”), as applied to claims 1 and 8 above, and in view of Kim et al. (US PG-Pub No. 2020/0373271 A1, hereinafter, “Kim”).
Regarding claim 3, Cho discloses the electronic package of claim 1.
Cho is silent regarding that the set of interconnect components are disposed around the second set of electronic components.
Kim, however, discloses an electronic package (see Kim, FIG. 9), wherein a set of interconnect components (210, FIG. 9) are disposed around a second set of electronic components (220, FIG. 9).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to form Cho’s set of interconnect components disposed around the second set of electronic components, as taught by Kim, in order to have multiple outside connections.
Regarding claim 13, Cho discloses the method of claim 8.
Cho is silent regarding that the set of interconnect components are disposed around the second set of electronic components.
Kim, however, discloses an electronic package (see Kim, FIG. 9), wherein a set of interconnect components (210, FIG. 9) are disposed around a second set of electronic components (220, FIG. 9).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to form Cho’s set of interconnect components disposed around the second set of electronic components, as taught by Kim, in order to have multiple outside connections.
Claims 6 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Cho et al. (US PG-Pub No.: 2022/0246533 A1, hereinafter, “Cho”), as applied to claims 1 and 8 above, and in view of Vincent et al. (US PG-Pub No. 2018/0005957 A1, hereinafter, “Vincent”).
Regarding claim 6, Cho discloses the electronic package of claim 1.
Cho is silent regarding a shielding layer disposed over the encapsulant layer, wherein the set of interconnect components further extend through the shielding layer, and at least a portion of the set of interconnect components are not electrically connected to the shielding layer.
Vincent, however, discloses an electronic package (see Vincent, FIG. 9), comprising a shielding layer (802, FIG. 9) disposed over an encapsulant layer (202, FIG. 9), wherein a set of interconnect components (112, FIG. 9) further extend through the shielding layer (802), and at least a portion of the set of interconnect components (112) are not electrically connected to the shielding layer (802, FIG. 2).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to form a shielding layer disposed over Cho’s encapsulant layer, wherein the set of interconnect components further extend through the shielding layer, and at least a portion of the set of interconnect components are not electrically connected to the shielding layer, as taught by Vincent, in order to eliminate influence of RF radiation.
Regarding claim 9, Cho discloses the method of claim 8.
Cho is silent regarding that before forming a set of openings through the encapsulant layer (13), forming a shielding layer over the encapsulant layer, wherein at least a portion of the set of interconnect components are not electrically connected to the shielding layer.
Vincent, however, discloses a method of forming an electronic package (see Vincent, FIG. 9), comprising forming a shielding layer (802, FIG. 9) over an encapsulant layer (202, FIG. 9), wherein at least a portion of a set of interconnect components (112, FIG. 9) are not electrically connected to the shielding layer (802, FIG. 9).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to form a shielding layer over the encapsulant layer, wherein at least a portion of the set of interconnect components are not electrically connected to the shielding layer, as taught by Vincent, in order to eliminate influence of RF radiation.
Claims 7 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Cho et al. (US PG-Pub No.: 2022/0246533 A1, hereinafter, “Cho”) in view of Vincent et al. (US PG-Pub No. 2018/0005957 A1, hereinafter, “Vincent”), as applied to claims 6 and 9 above, and further in view of Chen et al. (US PG-Pub No.: 2022/0262701 A1, hereinafter, “Chen”).
Regarding claim 7, Cho in view of Vincent discloses the electronic package of claim 6.
Cho in view of Vincent is silent regarding a heat dissipation lid attached onto the shielding layer in the first region.
However, it is well-known to add a heat dissipation lid on top of a semiconductor device. For example, Chen discloses an electronic package (see Chen, FIG. 1), comprising a heat dissipation lid (210, FIG. 1) attached to a semiconductor package (FIG. 1).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to form a heat dissipation lid attached onto the shielding layer in the first region in order to dissipate heat.
Regarding claim 10, Cho in view of Vincent discloses the method of claim 9.
Cho in view of Vincent is silent regarding attaching a heat dissipation lid onto the shielding layer in the first region.
However, it is well-known to add a heat dissipation lid on top of a semiconductor device. For example, Chen discloses a method of forming an electronic package (see Chen, FIG. 1), comprising attaching a heat dissipation lid (210, FIG. 1) to a semiconductor package (FIG. 1).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to form a heat dissipation lid attached onto the shielding layer in the first region in order to dissipate heat.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to XIA L. CROSS whose telephone number is (571)270-3273. The examiner can normally be reached 9 am-5:30 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at 571-272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/XIA L CROSS/Primary Examiner, Art Unit 2892