Prosecution Insights
Prosecution Insights
Technology area: Semiconductors, Circuits & Optics
5 pending office actions • 2 art units • 5 examiners • 0 of 5 (0%) have an AI response strategy ready • 11 patents granted in the last 365 days
Jcet Stats Chippac Korea Limited is currently managing 6 pending office actions within the Semiconductors, Circuits & Optics technology area. These 6 actions are distributed across 3 distinct art units, suggesting a moderately diverse range of technical subject matter within this field. The portfolio involves 6 distinct examiners, meaning that every pending action is being reviewed by a different individual. This distribution indicates that the company's prosecution strategy must account for a wide variety of examiner perspectives and requirements.
TYLER J WIEGAND is identified as the busiest examiner, though he is only responsible for 1 pending office action. This highlights the high degree of distribution in the portfolio, as the 6 pending office actions are spread evenly among 6 distinct examiners. Practitioners should prepare for a variety of examiner styles, even though the work is concentrated in only 3 distinct art units. The presence of 3 distinct art units alongside 6 distinct examiners suggests that while the technical focus is somewhat contained, the administrative review process is highly fragmented.
Based on the USPTO statutory response window for each pending office action. 1 of the docket's apps have a known mailing date; the rest are excluded from the tile counts.
Difficulty is derived from the rejection statutes on the most recent pending office action. §101-driven and multi-statute cases are graded Hard; §112-only and obviousness-type double-patenting cases are graded Easy; everything else is Medium. "Unknown" means we have not yet parsed a statute for that office action.
| Bucket | Cases |
|---|---|
| §103 only | 3 (60%) |
| Multi-statute (no §101) | 2 (40%) |
How the docket's pending cases split across USPTO tech-center bands.
Manual office-action response work runs about 10 hours per case. The time-saved bands below show what IP Author's prosecution pipeline typically delivers — a conservative 20% on the low end, 35% in the middle, 50% on the high end.
| Examiner | Apps on this docket | Allow rate | Interview lift |
|---|---|---|---|
| WIEGAND, TYLER J | 1 | 74.3% | +13.0% |
| MUNOZ, ANDRES F | 1 | 76.3% | +17.5% |
| TURNER, BRIAN | 1 | 83.4% | +4.4% |
| MAZUMDER, DIDARUL A | 1 | 86.5% | +7.8% |
| TOBERGTE, NICHOLAS J | 1 | 94.5% | +2.1% |
Cases in front of an examiner with an allow rate of 80%+ where the difficulty is Easy or Medium. The top 2 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18471960 | Semiconductor Device and Method of Forming Fine-Pitch Interconnection Using Insulating Layer | TOBERGTE, NICHOLAS J | 63d |
| 18597878 | SEMICONDUCTOR DEVICE WITH IMPROVED HEAT DISSIPATION AND METHOD FOR MAKING THE SAME | MAZUMDER, DIDARUL A | — |
Multi-statute / §101-driven matters, or cases in front of an examiner with an allow rate under 30%. The top 2 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18670747 | SEMICONDUCTOR PACKAGE WITH IMPROVED HEAT DISSIPATION | WIEGAND, TYLER J | — |
| 18636301 | SEMICONDUCTOR PACKAGE STRIP AND METHOD FOR FORMING A SEMICONDUCTOR DEVICE | TURNER, BRIAN | — |
Cases in front of an examiner whose interview lift is 10 percentage points or more — i.e. interviewed cases historically resolve more favorably than non-interviewed ones. The top 2 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18670747 | SEMICONDUCTOR PACKAGE WITH IMPROVED HEAT DISSIPATION | WIEGAND, TYLER J | — |
| 18639994 | SEMICONDUCTOR DEVICE WITH A PARTIAL SHIELDING LAYER AND A METHOD FOR MAKING THE SAME | MUNOZ, ANDRES F | — |
| Art Unit | Apps |
|---|---|
| 2812 | 1 |
| 2817 | 1 |
| App # | Title | Examiner | Art Unit | Statutes | Status | Due in | AI | Filed |
|---|---|---|---|---|---|---|---|---|
| 18670747 | SEMICONDUCTOR PACKAGE WITH IMPROVED HEAT DISSIPATION | WIEGAND, TYLER J | — | §102§112 | Non-Final OA | — | Pending | May 22, 2024 |
| 18639994 | SEMICONDUCTOR DEVICE WITH A PARTIAL SHIELDING LAYER AND A METHOD FOR MAKING THE SAME | MUNOZ, ANDRES F | — | §103 | Final Rejection | — | Pending | Apr 19, 2024 |
| 18636301 | SEMICONDUCTOR PACKAGE STRIP AND METHOD FOR FORMING A SEMICONDUCTOR DEVICE | TURNER, BRIAN | — | §102§103 | Final Rejection | — | Pending | Apr 16, 2024 |
| 18597878 | SEMICONDUCTOR DEVICE WITH IMPROVED HEAT DISSIPATION AND METHOD FOR MAKING THE SAME | MAZUMDER, DIDARUL A | 2812 | §103 | Final Rejection | — | Pending | Mar 06, 2024 |
| 18471960 | Semiconductor Device and Method of Forming Fine-Pitch Interconnection Using Insulating Layer | TOBERGTE, NICHOLAS J | 2817 | §103 | Non-Final OA | 63d | Pending | Sep 21, 2023 |
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