6 pending office actions • 5 art units • 6 examiners • 0 of 6 (0%) have an AI response strategy ready • 9 patents granted in the last 365 days
Based on the USPTO statutory response window for each pending office action. 2 of the docket's apps have a known mailing date; the rest are excluded from the tile counts.
Difficulty is derived from the rejection statutes on the most recent pending office action. §101-driven and multi-statute cases are graded Hard; §112-only and obviousness-type double-patenting cases are graded Easy; everything else is Medium. "Unknown" means we have not yet parsed a statute for that office action.
| Bucket | Cases |
|---|---|
| §103 only | 3 (50%) |
| Multi-statute (no §101) | 3 (50%) |
How the docket's pending cases split across USPTO tech-center bands.
Manual office-action response work runs about 10 hours per case. The time-saved bands below show what IP Author's prosecution pipeline typically delivers — a conservative 20% on the low end, 35% in the middle, 50% on the high end.
| Examiner | Apps on this docket | Allow rate | Interview lift |
|---|---|---|---|
| TRAN, TAN N | 1 | 86.8% | +10.0% |
| JONES, ERIC W | 1 | 62.1% | +17.1% |
| WEILAND, ADAM DAVID | 1 | 94.4% | +9.1% |
| CROSS, XIA L | 1 | 82.5% | +8.9% |
| TOBERGTE, NICHOLAS J | 1 | 94.6% | +1.9% |
| NETTLES, CORALIE ANN | 1 | 68.6% | +32.6% |
Cases in front of an examiner with an allow rate of 80%+ where the difficulty is Easy or Medium. The top 1 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18471960 | Semiconductor Device and Method of Forming Fine-Pitch Interconnection Using Insulating Layer | TOBERGTE, NICHOLAS J | 63d |
Multi-statute / §101-driven matters, or cases in front of an examiner with an allow rate under 30%. The top 3 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18395650 | ELECTRONIC DEVICE AND METHOD FOR MANUFACTURING THE SAME | TRAN, TAN N | — |
| 18482377 | Semiconductor Device and Method of Forming Embedded Trace Substrate with Barrier Layer to Inhibit Electromigration | WEILAND, ADAM DAVID | — |
| 18475249 | ELECTRONIC PACKAGE AND A METHOD FOR MAKING THE SAME | CROSS, XIA L | — |
Cases in front of an examiner whose interview lift is 10 percentage points or more — i.e. interviewed cases historically resolve more favorably than non-interviewed ones. The top 3 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18469536 | METHOD FOR MAKING AN ELECTRONIC PACKAGE | NETTLES, CORALIE ANN | 22d |
| 18395650 | ELECTRONIC DEVICE AND METHOD FOR MANUFACTURING THE SAME | TRAN, TAN N | — |
| 18493543 | Semiconductor Device and Method of Forming Flexible Encapsulant Over Thin Electrical Component | JONES, ERIC W | — |
| Art Unit | Apps |
|---|---|
| 2892 | 2 |
| 2812 | 1 |
| 2813 | 1 |
| 2817 | 1 |
| 2893 | 1 |
| App # | Title | Examiner | Art Unit | Statutes | Status | Due in | AI | Filed |
|---|---|---|---|---|---|---|---|---|
| 18395650 | ELECTRONIC DEVICE AND METHOD FOR MANUFACTURING THE SAME | TRAN, TAN N | 2812 | §102§103 | Non-Final OA | — | Pending | Dec 25, 2023 |
| 18493543 | Semiconductor Device and Method of Forming Flexible Encapsulant Over Thin Electrical Component | JONES, ERIC W | 2892 | §103 | Non-Final OA | — | Pending | Oct 24, 2023 |
| 18482377 | Semiconductor Device and Method of Forming Embedded Trace Substrate with Barrier Layer to Inhibit Electromigration | WEILAND, ADAM DAVID | 2813 | §102§112 | Non-Final OA | — | Pending | Oct 06, 2023 |
| 18475249 | ELECTRONIC PACKAGE AND A METHOD FOR MAKING THE SAME | CROSS, XIA L | 2892 | §102§103 | Final Rejection | — | Pending | Sep 27, 2023 |
| 18471960 | Semiconductor Device and Method of Forming Fine-Pitch Interconnection Using Insulating Layer | TOBERGTE, NICHOLAS J | 2817 | §103 | Non-Final OA | 63d | Pending | Sep 21, 2023 |
| 18469536 | METHOD FOR MAKING AN ELECTRONIC PACKAGE | NETTLES, CORALIE ANN | 2893 | §103 | Final Rejection | 22d | Pending | Sep 18, 2023 |
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