DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 4/30/2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-3, 5, 7-8 and 10-14 are rejected under 35 U.S.C. 103 as being unpatentable over Sasaki et al. (PG Pub. No. US 2020/0365509 A1) in view of Huang (PG Pub. No. US 2005/0242399 A1).
Regarding claim 1, Sasaki teaches an integrated circuit (figs. 6 & 7A-7B among others) comprising:
a plurality of gate lines (¶ 0030: GE) extending in a first horizontal direction over a substrate (fig. 6: plurality of GE lines extend in D1 direction over substrate SL);
first, second, third, and fourth active patterns (¶ 0022: FN1, FN2 in each region PR, NR) extending in a second horizontal direction intersecting the first horizontal direction over the substrate (figs. 6, 7A: FN1/FN2 patterns extend in D2 direction over SL);
a first pattern (¶ 0081: POR2 or POR1 of layer UML1) extending in the second horizontal direction (fig. 6: POR2/POR1 extends in D2 direction) over a region between the first active pattern and the second active pattern (fig. 6: POR2/POR1 extends in D2 direction between pair of NR/FN2 patterns), wherein the first pattern is configured to receive a first voltage (¶¶ 0038, 0084: POR2 and/or POR1 configured to receive VDD and/or VSS);
a second pattern (¶ 0081: POR1 or POR2 of UML1) extending in the second horizontal direction over a region between the third active pattern and the fourth active pattern (fig. 6: POR1 or POR2 extends in D2 direction between pair of PR/FN1 patterns), wherein the second pattern is configured to receive a second voltage (¶ 0038, 0084: POR1/POR2 configured to receive VDD and/or VSS);
a first well (¶ 0018: NR or PR) extending in the second horizontal direction over the substrate and overlapping the first active pattern and the second active pattern in a vertical direction (figs. 6 & 7B among others: NR/PR extending in D2 direction over SL and overlap FN1/FN2 in D3 direction);
at least one first via (¶ 0042: UVI) connected to the first pattern (figs.6, 7B: UVI electrically connected to POR2 or POR1) wherein the at least one first via is configured to provide the first voltage to the first well through a source/drain region (fig. 7B: UVI configured to provide POR1 or POR2 to NR or PR through SD1 or SD2), and the source/drain region is formed in the first active pattern or the second active pattern (figs. 6, 7B: SD1 or SD2 formed in FN1 or FN2); and
at least one second via (¶ 0021: TVI) passing through the substrate in a vertical direction (fig. 7A: TVI vertically passes through SL), and electrically connecting the second pattern to a first power line extending under the substrate (¶ 0046 & fig. 7A: TVI electrically connects POR1 or POR2 to LML1 of PON).
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Sasaki fails to teach the source/drain region formed in the first or second active pattern has a same conductivity type as the first well.
Huang teaches an integrated circuit device (figs. 1a-1b: 100) including a source/drain region (¶¶ 0017, 0041: 150/170) formed in an active region (active region of substrate 110, similar to active patterns of Sasaki), the source/drain region having a same conductivity type as a first well (¶ 0017: in at least one embodiment, portion 170 has same conductivity type as substrate well).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure at least a portion of the source/drain region of Sasaki with a same conductivity as the first well, as a means to provide and/or enhance electrostatic discharge protection (Huang, ¶ 0015).
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Regarding claim 2, Sasaki in view of Huang teaches the integrated circuit of claim 1, wherein the first pattern and the at least one first via are electrically connected to the first well (Sasaki, under device operation, POR2 and UVI electrically connected to well WD in region NR or PR).
Regarding claim 3, Sasaki in view of Huang teaches the integrated circuit of claim 2, wherein the first well overlaps the third active pattern and the fourth active pattern in the vertical direction (Sasaki, FN2 formed in well WD of second region NR, and/or FN1 formed in well WD of first region PR), and the at least one second via passes through the first well (Sasaki, fig. 2B: TVI passes through well WD between FN2 regions or through well WD between FN1 regions).
Regarding claim 5, Sasaki in view of Huang teaches the integrated circuit of claim 1, further comprising:
a fifth active pattern extending in the second horizontal direction over the substrate, the fifth active pattern being adjacent to the fourth active pattern (Sasaki, figs. 1, 2A-2C: 1st active pattern FN1 in region PR extends in D2 direction and adjacent to FN2 in region NR);
a sixth active pattern extending in the second horizontal direction over the substrate, the sixth active pattern being adjacent to the fifth active pattern (Sasaki, figs. 1, 2A-2C: 2nd active pattern FN1 in region PR);
a third pattern (Sasaki, portion BP of AC in region PR) extending in the second horizontal direction over a region between the fifth active pattern and the sixth active pattern (Sasaki, fig. 1: AC extends in D2 direction and between active patterns FN1), wherein the third pattern is configured to receive the first voltage (Sasaki, fig. 2B: BP in region PR electrically connected to ULM1 and/or ULM2); and
at least one third via (Sasaki, EP between regions PR) contacting the third pattern (Sasaki, fig. 2B: EP between FN1 electrically contacts BP) and electrically connecting the third pattern to a second power line extending under the substrate (Sasaki, ¶ 0038 & fig. 2B: EP between FN1 electrically connects BP to second LML1 under SL; POR1 configured with voltage VDD).
Regarding claim 7, Sasaki in view of Huang teaches the integrated circuit of claim 1, wherein each of the at least one second via passes through the substrate in a vertical direction between two adjacent gate lines of the plurality of gate lines (Sasaki, figs. 1, 2B: TVI passes through SL between adjacent GE).
Regarding claim 8, Sasaki in view of Huang teaches the integrated circuit of claim 1, wherein portions of the second active pattern adjacent to the at least one first via and portions of the third active pattern adjacent to the at least one second via have a same conductive type (Sasaki, each FN2 configured as channel regions of n-type devices, and therefore have same conductive type).
Regarding claim 10, Sasaki in view of Huang teaches the integrated circuit of claim 1,
wherein the first pattern and the second pattern are in a first wiring layer closest to the plurality of gate lines (Sasaki, figs. 2A-2C: patterns in UML1 closest to wiring layer to GE).
Regarding claim 11, Sasaki teaches an integrated circuit (figs. 6, 7A-7B) comprising:
a plurality of gate lines (¶ 0030: GE) extending in a first horizontal direction over a substrate (figs. 6, 7A-7B: plurality of GE extending in D1 direction on substrate SL);
first, second, third, and fourth active patterns (¶ 0022: at least 4 active patterns FN1 and/or FN2) extending in a second horizontal direction intersecting the first horizontal direction over the substrate (figs. 6, 7A-7B: FN1/FN2 extend in direction D2);
a first pattern (¶ 0036: UML1) extending in the second horizontal direction (fig. 7A: UML1 extends in D2 direction) over a region between the first active pattern and the second active pattern (at least one UML1 extends in D2 direction between pair of FN1 and/or FN2 patterns), wherein the first pattern is configured to receive a first voltage (¶¶ 0038, 0043: UML1 comprises metal and connected to a source/drain region of an active device, and therefore is implicitly configured to receive a voltage applied to the source/drain region during device operation);
a second pattern (¶ 0020: POR1, POR2 and/or UVI) extending in the second horizontal direction over a region between the third active pattern and the fourth active pattern (fig. 7: POR1/POR2 extends in direction D2 between at least two active fins FN1 and/or FN2), wherein the second pattern is configured to receive a second voltage (POR1 electrically connected to power network POR);
a first well (¶ 0018: NR or PR) extending in the second horizontal direction over the substrate and overlapping the first active pattern and the second active pattern in a vertical direction (figs. 6 & 7B among others: NR/PR extending in D2 direction over SL and overlap FN1/FN2 in D3 direction);
a first via (¶ 0021: first TVI) passing through the substrate in a vertical direction and electrically connecting the first pattern to a first power line extending under the substrate (¶ 0021, fig. 7A: TVI passes through SL and electrically connects to LML1 of power network POR);
a second via (second TVI) passing through the substrate in the vertical direction and electrically connecting the second pattern to a second power line extending under the substrate (fig. 7A: second TVI passes through SL and connects POR1/POR2/UVI to second LML1 of POR); and
at least one third via (fig.7B: third UVI) connected to the first pattern (fig. 7B: third UVI connected to UML1), wherein the at least one third via is configured to provide the first voltage to the first well through a source/drain region (fig. 7B: third UVI provides voltage to NR and/or PR regions through SD1 and/or SD2), and the source/drain region is formed in the first active pattern or the second active pattern (figs. 7A-7B: SD1 or SD2 formed in region PR or NR).
Sasaki fails to teach the source/drain region formed in the first or second active pattern has a same conductivity type as the first well.
Huang teaches an integrated circuit device (figs. 1a-1b: 100) including a source/drain region (¶ 0014: 150/170) formed in an active region (active region of substrate 110), the source/drain region having a same conductivity type as a first well (¶ 0014: 170 has same conductivity type as substrate p-well).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure at least a portion of the source/drain region of Sasaki with a same conductivity as the first well, as a means to provide and/or enhance electrostatic discharge protection (Huang, ¶ 0015).
Regarding claim 12, Sasaki in view of Huang teaches the integrated circuit of claim 11,
wherein the gate lines comprise first, second, and third gate lines (Sasaki, fig. 6: at least 3 gate lines GE),
wherein the first via passes through the first gate line in the vertical direction between the second gate line and the third gate line, which are each adjacent to the first gate line (Sasaki, figs. 6, 7A-7B: first TVI passes through pattern including first GE, second and third GE adjacent to first GE), and
the second via passes through the first gate line in the vertical direction between the second gate line and the third gate line (Sasaki, figs. 6, 7A-7B: second TVI passes through pattern including first GE in vertical direction).
Regarding claim 13, Sasaki in view of Huang teaches the integrated circuit of claim 12, wherein respective portions of the first, second, third, and fourth active patterns are cut between the second gate line and the third gate line (figs. 6, 7A-7B: portions of active regions cut to form active fins FN1 and/or FN2 between second and third GE).
Regarding claim 14, Sasaki teaches the integrated circuit of claim 11, further comprising:
at least one third via (Sasaki, ¶ 0041: UVI) contacting the first pattern and electrically connecting the first pattern to one or more devices comprising the first active pattern and the second active pattern (Sasaki, figs. 7A-7B: at least one UVI electrically connects POR1 to active patterns FN1 and/or FN2);
and at least one fourth via (Sasaki, second UVI) contacting the second pattern and electrically connecting the second pattern to one or more bodies of devices comprising at least a portion of the third active pattern or the fourth active pattern (Sasaki, figs. 7A-7B: second UVI electrically connects POR2 to second active patterns FN1 and/or FN2).
Claims 19-21 are rejected under 35 U.S.C. 3 as being unpatentable over Shen et al. (PG Pub. No. US 2022/0285434 A1) in view of Huang.
Regarding claim 19, Shen teaches an integrated circuit (fig. 3A among others) comprising:
a bit cell array including a plurality of bit cells (¶¶ 0023, 0031: 100, including array of memory cells MC); and
a peripheral region (¶ 0040: 200) including a peripheral circuit (220), wherein the peripheral region comprises:
a plurality of devices (¶ 0034: D2) over a substrate (¶ 0033, fig. 3A: D2 disposed over substrate 210);
a first well over the substrate and overlapping at least one of the plurality of devices in a vertical direction (¶ 0034: D2 configured as FET devices, and therefore implicitly include well regions in substrate 210);
at least one pattern (¶ 0035: 224-1 through 224-5) configured to provide a first voltage to at least one of the plurality of devices (¶ 0035 & fig. 2B: 224-1/224-5 electrically connected to gate 212b and/or source/drain 214 of devices D2, and therefore implicitly configured to provide a voltage);
at least one power line (¶ 0049: lines of power supply network in circuit structure 300) extending under the substrate (fig. 3B: 300 extends under 210); and
at least one first via (¶ 0036: first TV) passing through the substrate in a vertical direction in the peripheral region (fig. 3B: TV vertically passes through 210 in 200) and electrically connecting the at least one pattern to the at least one power line (fig. 3B: at least one 224-1 through 224-5 electrically connected to 300 by TV);
at least one second via (second TV) connected to the at least one pattern (figs. 2B, 3B: second TV electrically connected to at least one 224-1 through 224-5), wherein the at least one second via is configured to provide the first voltage to the first well through a source/drain region (fig. 3B: second TV configured to provide voltage to well region of D2 through source/drain region 214), and the source/drain region is formed in at least one of the plurality of devices.
Shen does not teach wherein the source/drain region has a same conductivity type as the first well.
Huang teaches an integrated circuit device (figs. 1a-1b: 100) including a source/drain region (¶ 0014: 150/170) formed in an active region (active region of substrate 110), the source/drain region having a same conductivity type as a first well (¶ 0014: 170 has same conductivity type as substrate p-well).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure at least a portion of the source/drain region of Shen with a same conductivity as the first well, as a means to provide and/or enhance electrostatic discharge protection (Huang, ¶ 0015).
Regarding claim 20, Shen in view of Huang teaches the integrated circuit of claim 19, further comprising:
at least one third via (Shen, fig. 3B: third TV) passing through the substrate in the vertical direction and electrically connecting the at least one pattern to the at least one power line (Shen, fig. 3A: at least a third TV passes through 210 and electrically connected to 300), the at least one third via being adjacent to a boundary between the bit cell array and the peripheral region (Shen, fig. 3A: third TV adjacent to boundary between 100 and 200).
Regarding claim 21, Shen in view of Huang teaches the integrated circuit of claim 19, wherein the peripheral region comprises a plurality of sub-regions respectively corresponding to a plurality of circuits included in the peripheral circuit (Shen, fig. 3A: 200 includes plurality of subregions), and
the at least one first via is adjacent to boundaries between the plurality of sub-regions (Shen, fig. 3A: first TV adjacent to boundary between subregions of 200).
Claims 4, 6 and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Sasaki in view of Huang as applied to claims 5 and 14 above, and further in view of Zhou (PG Pub. No. US 2019/0199339 A1).
Regarding claims 4 and 16, Sasaki in view of Huang teaches the integrated circuit of claims 5 and 14, comprising a first pattern, at least one first via and a substrate.
Sasaki in view of Huang does not teach wherein the first pattern and the at least one first via are electrically connected to the substrate.
Zhou teaches an integrated circuit (figs. 2-3 among others) wherein a first voltage (VSS) is connected to a first well in a substrate (¶ 0036, fig. 3: body of 309 and 311 connected to VSS).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the first pattern and the at least one first via of Sasaki in view of Huang to be electrically connected to the substrate, as a means to provide VSS voltage to a well, allowing for optimization of a body effect and threshold voltage control.
Regarding claims 6 and 15, Sasaki in view of Huang teaches the integrated circuits of claims 5 and 14, comprising a first well (Sasaki, ¶ 0047: well dopant WL disposed in SL).
Sasaki in view of Huang does not explicitly teach wherein the first pattern and the at least one first via are electrically connected to the first well.
Zhou teaches an integrated circuit (figs. 2-3 among others) wherein a first voltage (VSS) is connected to a first well (¶ 0036, fig. 3: body of 309 and 311 connected to VSS).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the first pattern and the at least one first via of Sasaki in view of Huang to be electrically connected to the first well, as a means to provide VSS voltage to the first well, allowing for optimization of a body effect and threshold voltage control.
Claims 9 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Sasaki in view of Huang as applied to claims 1 and 11 above, and further in view of Shen.
Regarding claims 9 and 17, Sasaki in view of Huang teaches the integrated circuits of claims 1 and 11, comprising a plurality of gate lines (Sasaki, GE), at least one first via (Sasaki, UVI) and at least one second via (Sasaki, EP).
Sasaki in view of Huang does not teach wherein the plurality of gate lines comprise:
a first gate line group crossing devices included in a bit cell array; and
a second gate line group crossing devices included in a peripheral circuit, and
the at least one first via and the at least one second via are in a peripheral region comprising the peripheral circuit.
Shen teaches an integrated circuit (fig. 3A among others) including:
a plurality of gate lines (¶¶ 0034: 212a, 212b) comprising:
a first gate line group (112b) crossing devices included in a bit cell array (¶ 0023 & fig. 3A: 112b crosses devices included in cell array 100); and
a second gate line group (212b) crossing devices included in a peripheral circuit (fig. 3A: 212b crosses devices included in peripheral circuit region 200), and
at least one first via and at least one second via (¶¶ 0035-0036: 2128, TV) are in a peripheral region comprising the peripheral circuit (fig. 3A: 218, TV disposed in region comprising 200).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the integrated circuit of Sasaki in view of Huang with the gate line groups of Shen, as a means to avoid current resistance drop, voltage fluctuation and noise on the power supply network (Shen, ¶ 0030).
Response to Arguments
Applicant’s arguments with respect to claims 1-13, 15-17 and 19-21 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/BRIAN TURNER/Examiner, Art Unit 2818
