Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgment
The amendment filed on 05/05/2026 has been entered. The present Office action is made with all the suggested amendments being fully considered. Accordingly, pending in this application are claims 1-20.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-13 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-4, 6-9, 12-13 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Anderson et al. (US 20240172408 A1; hereinafter “Anderson”).
In re claim 1, Anderson discloses in figs. 1-5, 7, an integrated circuit device comprising:
an upper transistor structure 40-1 on a substrate 610 (¶57),
the upper transistor structure 40-1 comprising a pair of upper source/drain regions 120, 120 (¶23) spaced apart from each other in a first horizontal direction (e.g., north-south direction in fig. 4-1; hereinafter D1) and an upper gate electrode 110/635 in 40-1 (¶23) between the pair of upper source/drain regions 120, 120;
a lower transistor structure 50-1 (¶51) between the substrate 610 and the upper transistor structure 40-1,
the lower transistor structure 50-1 comprising a lower gate electrode (635 in the NFET layer 405) (hereinafter “L_GE”) (¶58);
an upper insulating layer (upper insulating layer 620) (fig. 7; ¶58) on the lower transistor structure 50-1,
wherein the upper gate electrode (635 in the PFET layer 480) is in the upper insulating layer 620; and
a lower gate contact 710 (¶63) extending through the upper insulating layer (i.e., upper insulating layer 620) and contacting the lower gate electrode (635 in the NFET layer 405),
wherein the lower gate contact 710 and the lower gate electrode (635 in the NFET layer 405) have an interface therebetween (fig. 7),
wherein a center of the upper gate electrode (635 in the PFET layer 480) in a second horizontal direction (e.g., east-west direction in figs. 4-1, 7; hereinafter D2) and a center of the lower gate electrode (635 in the NFET layer 405) in the second horizontal direction D2 are offset from each other in the second horizontal direction D2 (fig. 7 shows a center of the upper gate electrode is offset from a center of the lower gate electrode), and
wherein the second horizontal direction D2 is perpendicular to the first horizontal direction D1.
In re claim 2, Anderson discloses in figs. 1-5, 7, the integrated circuit device of Claim 1, wherein the lower gate electrode (635 in the lower left transistor 50-1) comprises a first portion (e.g., a rightmost portion) that is not overlapped by the upper gate electrode (635 in the upper left transistor 40-1)and a second portion (e.g., a leftmost portion) that is overlapped by the upper gate electrode.
In re claim 3, Anderson discloses in figs. 1-5, 7, the integrated circuit device of Claim 2. wherein the upper gate electrode (635 in the lower left transistor 50-1) comprises a first portion (e.g., a leftmost portion) that is not overlapped by the lower gate electrode (635 in the lower left transistor 50-1) and a second portion (e.g., a rightmost portion) that is overlapped by the lower gate electrode.
In re claim 4, Anderson discloses in figs. 1-5, 7, the integrated circuit device of Claim 2, wherein the lower gate contact 710 is in contact with the first portion of the lower gate electrode (i.e., the rightmost portion of the lower gate electrode 635 in the lower transistor 40-1).
In re claim 6, Anderson discloses in figs. 1-5, 7, the integrated circuit device of Claim 1,
wherein the upper transistor structure is a first upper transistor (e.g., the upper left transistor 40-1), and the upper gate electrode is a first upper gate electrode 635 (hereinafter “U_GE1),
the integrated circuit device further comprises a second upper transistor (e.g., an upper right transistor 40-1) comprising a second upper gate electrode 635 (hereinafter U_GE2) that is spaced apart from the first upper gate electrode in the second horizontal direction D2,
wherein the lower gate contact 710 extends between the first upper gate electrode (U_GE1) and the second upper gate electrode (U_GE2).
In re claim 7, Anderson discloses in figs. 1-5, 7, the integrated circuit device of Claim 6, further comprising an intergate insulator 620, 615 (¶58) extending between the lower gate electrode (L_GE) and the first and second upper gate electrodes (U_GE1, U_GE2),
wherein the lower gate contact 710 extends through the intergate insulator 620, 615.
In re claim 8, Anderson discloses in figs. 1-5, 7, the integrated circuit device of Claim 1, wherein the first upper transistor structure 40-1 further comprises a first upper channel region 650 (¶58), and the lower transistor structure 50-1 further comprises a lower channel region 650, and a center of the first upper channel region (650 in the upper left transistor 40-1) in the horizontal direction D1 and a center of the lower channel region (650 in the lower left transistor 50-1)in the horizontal direction D1 are offset from each other in the horizontal direction D1.
In re claim 9, Anderson discloses in figs. 1-5, 7, an integrated circuit device comprising:
first and second upper transistor structures 40-1, 40-1 that are on a substrate 610 (¶57) and are spaced apart from each other in a horizontal direction (e.g., east-west direction; hereinafter D1),
the first and second upper transistor structures 40-1, 40-1 comprising first and second upper gate electrodes 635, 635 in the PFET layer 480, respectively (¶58);
a lower transistor structure 50-1 (¶51) between the substrate 610 and the first and second upper transistor structures 40-1, 40-1,
the lower transistor structure 50-1 comprising a lower gate electrode 635 in the NFET layer 405 (¶58) that comprises a portion (e.g., a rightmost portion in fig. 7) not overlapped by the first and second upper gate electrodes 40-1, 40-1;
an intergate insulator 615, 620 (¶58) extending between the lower gate electrode 635 in the NFET layer 405 and the first and second upper gate electrodes 635, 635 in the PFET layer 480; and
a lower gate contact 710 (¶63) between the first and second upper gate electrodes 635, 635 in the PFET layer 480,
the lower gate contact 710 extending through the intergate insulator 615, 620 and is in contact with the portion of the lower gate electrode 635 in the NFET layer 405 with an interface therebetween (see fig. 7).
In re claim 12, Anderson discloses in figs. 1-5, 7, the integrated circuit device of Claim 9, wherein the first upper transistor structure 40-1 further comprises a first upper channel region 650 (¶58), and the lower transistor structure 50-1 further comprises a lower channel region 650, and a center of the first upper channel region (650 in the upper left transistor 40-1) in the horizontal direction D1 and a center of the lower channel region (650 in the lower left transistor 50-1)in the horizontal direction D1 are offset from each other in the horizontal direction D1.
In re claim 13, Anderson discloses in figs. 1-5, 7, the integrated circuit device of Claim 12, wherein a center of the first upper gate electrode (635 in the upper left transistor 40-1) in the horizontal direction D1 and a center of the lower gate electrode (635 in the lower left transistor 50-1) in the horizonal direction D1 are offset from each other in the horizontal direction D1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5, 10-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Anderson, as applied to claims 1 and 9 above, respectively and further in view of Gardner et al. (US 20230056372 A1; hereinafter “Gardner”).
In re claim 5, Anderson discloses in figs. 1-5, 7, the integrated circuit device of Claim 1, further comprising an intergate insulator 615, 620 (¶58) extending between the lower gate electrode 635 in the NFET layer 405 and the first and second upper gate electrodes 635, 635 in the PFET layer 480.
Anderson does not expressly disclose
wherein the lower gate electrode comprises a lower metal gate layer and a lower work function layer, and
the lower work function layer extends between the intergate insulator and the lower metal gate layer.
In the same field of endeavor, Gardner discloses in figs. 1A-1C, an integrated circuit wherein a lower gate electrode 114 comprises a lower metal gate layer and a lower work function layer (Gardner discloses work function layer 114 can be made up of two or more layers of metals having different work functions; ¶54. Therefore, the inner metal layer of 114 has been interpreted as a lower metal gate layer and the outer metal layer of 114 has been interpreted as a lower work function layer),
the lower work function layer (i.e., the outer metal layer of 114) extends between an intergate insulator 137, 131 and the lower metal gate layer (i.e., the inner metal layer of 114).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to dispose a lower work function layer in the lower gate electrode of Anderson extending between the intergate insulator and the lower metal gate layer based on Gardner’s teachings in order to enable precise threshold voltage tuning and enhancing device performance.
In re claim 10, Anderson discloses the integrated circuit device of claim 9 outlined above.
Anderson does not expressly disclose wherein the lower gate electrode comprises a lower metal gate layer and a lower work function layer, and the lower work function layer extends between the intergate insulator and the lower metal gate layer.
In the same field of endeavor, Gardner discloses in figs. 1A-1C, an integrated circuit wherein a lower gate electrode 114 comprises a lower metal gate layer and a lower work function layer (Gardner discloses work function layer 114 can be made up of two or more layers of metals having different work functions; ¶54. Therefore, the inner metal layer of 114 has been interpreted as a lower metal gate layer and the outer metal layer of 114 has been interpreted as a lower work function layer),
the lower work function layer (i.e., the outer metal layer of 114) extends between an intergate insulator 137, 131 and the lower metal gate layer (i.e., the inner metal layer of 114).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to dispose a lower work function layer in Anderson extending between the intergate insulator and a lower metal gate layer based on Gardner’s teachings to enable precise threshold voltage tuning and enhance device performance.
In re claim 11, Anderson, as modified by Gardner, discloses the integrated circuit device of Claim 10, wherein the lower work function layer contacts (i.e., the outer metal layer of 114 in fig. 1C of Gardner) the intergate insulator (Anderson: 615, 620 in fig. 7).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NILUFA RAHIM whose telephone number is (571)272-8926. The examiner can normally be reached M-F 9am-5:30pm EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara J. Green can be reached at (571) 270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NILUFA RAHIM/Primary Examiner, Art Unit 2893
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