Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 09/15/2026 has been entered.
Acknowledgment
The amendment filed on 09/15/2026 has been entered. The present Office action is made with all the suggested amendments being fully considered. Accordingly, pending in this application are claims 1-20.
Response to Arguments
Applicant's arguments filed 09/15/2026 have been fully considered but they are not persuasive.
Applicant argues “FIG. 7 illustrates that element 110/635 is in contact with element 710. In addition, paragraph [0063] of Anderson clearly describes that element 710 is implemented for the electrical connection between elements 110/635. Therefore, Anderson fails to disclose, teach, or suggest an insulator between element 110/635 and element 710 in a horizontal direction, as recited in Claims 1 and 9”.
Examiner disagrees with the arguments presented above. The upper transistor has now been interpreted as the upper right PU1, 40-1 in the cell 401-2 which is included in the integrated device 600. In this new interpretation, a contact insulator 640 between the upper gate electrode (635 in the PFET layer 480 of the cell 401-2) and the lower gate contact (710 in cell 401-1) in a second horizontal direction (e.g., east-west direction in figs. 4-1, 7; hereinafter D2) (fig. 7, ¶57-58). Therefore, Anderson still teaches claim 1 and the rejection for claim 1 and dependent claims 5-8 stand.
Regarding claims 2-4 and 9-13, the arguments are persuasive.
Anderson, alone or in combination with other prior art, does not expressly disclose a second portion that is overlapped by the upper gate electrode, in combination with all other limitations cited in claims 1 and 2.
Anderson, alone or in combination with other prior art, does not expressly disclose a second contact insulator between the second upper gate electrode and the lower gate contact in the horizontal direction, in combination with all other limitations cited in claim 9.
Therefore, claims 2-4 and 9-13 are indicated allowable in this Office action.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 6-8 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Anderson et al. (US 20240172408 A1; hereinafter “Anderson”).
In re claim 1, Anderson discloses in figs. 1-5, 7, an integrated circuit device comprising:
an upper transistor structure (the upper right PU1, 40-1) on a substrate 610 (¶20, 57),
the upper transistor structure 40-1 comprising a pair of upper source/drain regions 120, 120 (¶23) spaced apart from each other in a first horizontal direction (e.g., north-south direction in fig. 4-1; hereinafter D1) and an upper gate electrode (fig. 7, 110/635 in the upper right PU1, 40-1) (¶23) between the pair of upper source/drain regions 120, 120;
a lower transistor structure (fig. 7, 50-1 in the cell 401-1) (¶51) between the substrate 610 and the upper transistor structure 40-1,
the lower transistor structure 50-1 comprising a lower gate electrode (fig. 7, 635 in the NFET layer 405 in cell 401-1) (hereinafter “L_GE”) (¶58);
an upper insulating layer (upper insulating layer 620) (fig. 7; ¶58) on the lower transistor structure 50-1,
wherein the upper gate electrode (635 in the PFET layer 480 of the cell 401-2) is in the upper insulating layer 620;
a lower gate contact (710 in cell 401-1) (fig. 7, ¶63) extending through the upper insulating layer (i.e., upper insulating layer 620) and contacting the lower gate electrode (635 in the NFET layer 405), and
a contact insulator 640 between the upper gate electrode (635 in the PFET layer 480 of the cell 401-2) and the lower gate contact 710 in a second horizontal direction (e.g., east-west direction in figs. 4-1, 7; hereinafter D2) (fig. 7, ¶57-58),
wherein the lower gate contact 710 and the lower gate electrode (635 in the NFET layer 405) have an interface therebetween (fig. 7),
wherein a center of the upper gate electrode (635 in the PFET layer 480 of the cell 401-2) in the second horizontal direction D2 and a center of the lower gate electrode (635 in the NFET layer 405 in cell 401-1) in the second horizontal direction D2 are offset from each other in the second horizontal direction D2 (fig. 7 shows a center of the upper gate electrode is offset from a center of the lower gate electrode), and
wherein the second horizontal direction D2 is perpendicular to the first horizontal direction D1.
In re claim 6, Anderson discloses in figs. 1-5, 7, the integrated circuit device of Claim 1,
wherein the upper transistor structure is a first upper transistor (e.g., the upper right transistor 40-1), and the upper gate electrode is a first upper gate electrode 635 (hereinafter “U_GE1),
the integrated circuit device further comprises a second upper transistor (e.g., an upper left transistor 40-1) comprising a second upper gate electrode 635 (hereinafter U_GE2) that is spaced apart from the first upper gate electrode in the second horizontal direction D2,
wherein the lower gate contact 710 extends between the first upper gate electrode (U_GE1) and the second upper gate electrode (U_GE2).
In re claim 7, Anderson discloses in figs. 1-5, 7, the integrated circuit device of Claim 6, further comprising an intergate insulator (lower coating layer of material 620, 615) (¶58) extending between the lower gate electrode (L_GE) and the first and second upper gate electrodes (U_GE1, U_GE2),
wherein the lower gate contact 710 extends through the intergate insulator 620, 615.
In re claim 8, Anderson discloses in figs. 1-5, 7, the integrated circuit device of Claim 1,
wherein the first upper transistor structure 40-1 further comprises a first upper channel region 650 (¶58), and
the lower transistor structure 50-1 further comprises a lower channel region 650, and
a center of the first upper channel region (650 in the upper left transistor 40-1) in the horizontal direction D1 and a center of the lower channel region (650 in the lower left transistor 50-1) in the second horizontal direction D2 are offset from each other in the second horizontal direction D2.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Anderson, as applied to claim 1 and further in view of Gardner et al. (US 20230056372 A1; hereinafter “Gardner”).
In re claim 5, Anderson discloses in figs. 1-5, 7, the integrated circuit device of Claim 1, further comprising an intergate insulator 615, 620 (¶58) extending between the lower gate electrode 635 in the NFET layer 405 and the first and second upper gate electrodes 635, 635 in the PFET layer 480.
Anderson does not expressly disclose:
wherein the lower gate electrode comprises a lower metal gate layer and a lower work function layer, and
the lower work function layer extends between the intergate insulator and the lower metal gate layer.
In the same field of endeavor, Gardner discloses in figs. 1A-1C, an integrated circuit wherein a lower gate electrode 114 comprises a lower metal gate layer and a lower work function layer (Gardner discloses work function layer 114 can be made up of two or more layers of metals having different work functions; ¶54. Therefore, the inner metal layer of 114 has been interpreted as a lower metal gate layer and the outer metal layer of 114 has been interpreted as a lower work function layer), the lower work function layer (i.e., the outer metal layer of 114) extends between an intergate insulator 137, 131 and the lower metal gate layer (i.e., the inner metal layer of 114).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to dispose a lower work function layer in the lower gate electrode of Anderson extending between the intergate insulator and the lower metal gate layer based on Gardner’s teachings in order to enable precise threshold voltage tuning and enhancing device performance.
Allowable Subject Matter
Claims 9-13 are allowed.
Claims 2-4 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
In re claim 2, Anderson discloses in figs. 1-5, 7, the integrated circuit device of Claim 1, wherein the lower gate electrode (635 in the lower left transistor 50-1) comprises a first portion (e.g., a left most portion) that is not overlapped by the upper gate electrode (635 in the upper right transistor 40-1).
Anderson, alone or in combination with other prior art, does not expressly disclose a second portion that is overlapped by the upper gate electrode, in combination with all other limitations cited in claims 1 and 2.
Dependent claims 3-4 are indicated allowable based on their dependency on claim 2.
In re claim 9, Anderson discloses in figs. 1-5, 7, an integrated circuit device comprising:
first and second upper transistor structures 40-1, 40-1 that are on a substrate 610 (¶57) and are spaced apart from each other in a horizontal direction (e.g., east-west direction; hereinafter D1),
the first and second upper transistor structures 40-1, 40-1 comprising first and second upper gate electrodes 635, 635 in the PFET layer 480, respectively (¶58);
a lower transistor structure 50-1 (¶51) between the substrate 610 and the first and second upper transistor structures 40-1, 40-1,
the lower transistor structure 50-1 comprising a lower gate electrode 635 in the NFET layer 405 (¶58) that comprises a portion (e.g., a rightmost portion in fig. 7) not overlapped by the first and second upper gate electrodes 40-1, 40-1;
an intergate insulator 615, 620 (¶58) extending between the lower gate electrode 635 in the NFET layer 405 and the first and second upper gate electrodes 635, 635 in the PFET layer 480; and
a lower gate contact 710 (¶63) between the first and second upper gate electrodes 635, 635 in the PFET layer 480,
the lower gate contact 710 extending through the intergate insulator 615, 620 and is in contact with the portion of the lower gate electrode 635 in the NFET layer 405 with an interface therebetween (see fig. 7);
a first contact insulator 640 between the first upper gate electrode 40-1 and the lower gate contact 710 in the horizontal direction D2.
Anderson, alone or in combination with other prior art, does not expressly disclose a second contact insulator between the second upper gate electrode and the lower gate contact in the horizontal direction, in combination with all other limitations cited in claim 9.
Dependent claims 10-13 are indicated allowable based on their dependency on claim 10.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NILUFA RAHIM whose telephone number is (571)272-8926. The examiner can normally be reached M-F 9am-5:30pm EST.
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/NILUFA RAHIM/Primary Examiner, Art Unit 2893
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