Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I, claims 1-13, in the reply filed on 01/28/2026 is acknowledged.
Claims 14-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention II, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 01/28/2026.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-4, 6-9, and 12-13 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Xie et al. (US 20230411386 A1; hereinafter “Xie”).
In re claim 1, Xie discloses in figs. 1, 23-48, an integrated circuit device comprising:
an upper transistor structure on a substrate 305 (an upper transistor structure formed in the top active region having a top gate region as shown in fig. 1. Hereinafter an upper transistor structure will be labeled as “TopFET1”) (¶91, 116),
the upper transistor structure TopFET1 comprising a pair of upper source/drain regions 375, 375 spaced apart from each other in a first horizontal direction (a first horizontal direction is a direction which extends from left to the right in fig. 45-48; hereinafter “X”) (fig. 45; ¶127) and an upper gate electrode 395 (hereinafter “Upper_GE1”) between the pair of upper source/drain regions 375, 375 (fig. 46-47; ¶136, 137);
a lower transistor structure (a lower transistor structure formed in the bottom active region having a bottom gate region as shown in fig. 1. Hereinafter a lower transistor structure will be labeled as “BottomFET1”) between the substrate 305 and the upper transistor structure TopFET1, the lower transistor structure comprising a lower gate electrode 395 (fig. 46-47; ¶136, 137) (hereinafter “Lower_GE1”);
an upper insulating layer 365 on the lower transistor structure BottomFET1, wherein the upper gate electrode Upper_GE1 is in the upper insulating layer 365 (¶125); and
a lower gate contact extending through the upper insulating layer 350 and contacting the lower gate electrode 395 (see fig. 47, a lower gate contact has been interpreted as a contact between middle two spacers 365 contacting a lower gate of the device 440; ¶137. Hereinafter “Lower_CB1”),
wherein a center of the upper gate electrode Upper_GE1 in a second horizontal direction Y and a center of the lower gate electrode Lower_GE1 in the second horizontal direction Y are offset from each other in the second horizontal direction Y (as shown in fig. 47 annotated below), and
the second horizontal direction Y is perpendicular to the first horizontal direction X.
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In re claim 2, Xie discloses in figs. 1, 23-48, the integrated circuit device of Claim 1, wherein the lower gate electrode Lower_GE1 comprises a first portion (e.g., a middle portion of the lower gate electrode 395) that is not overlapped by the upper gate electrode Upper_GE1 and a second portion (e.g., a left edge portion of the lower gate electrode 395) that is overlapped by the upper gate electrode Upper_GE1.
In re claim 3, Xie discloses in figs. 1, 23-48, the integrated circuit device of Claim 2. wherein the upper gate electrode Upper_GE1 comprises a first portion (e.g., a middle portion of the upper gate electrode 395) that is not overlapped by the lower gate electrode Lower_GE1 and a second portion (e.g., a right edge portion of the upper gate electrode 395) that is overlapped by the lower gate electrode.
In re claim 4, Xie discloses in figs. 1, 23-48, the integrated circuit device of Claim 2, wherein the lower gate contact Lower_CB1 is in contact with the first portion of the lower gate electrode (i.e., the middle portion of the lower gate electrode 395).
In re claim 6, Xie discloses in figs. 1, 23-48, the integrated circuit device of Claim 1, wherein the upper transistor structure is a first upper transistor, and the upper gate electrode is a first upper gate electrode,
the integrated circuit device further comprises a second upper transistor 435 comprising a second upper gate electrode Upper_GE2 that is spaced apart from the first upper gate electrode Upper_GE1 in the second horizontal direction Y (¶137),
wherein the lower gate contact Lower_CB1 extends between the first upper gate electrode (Upper_GE1) and the second upper gate electrode (Upper_GE2) (see fig. 47 annotated below).
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In re claim 7, Xie discloses in figs. 1, 23-48, the integrated circuit device of Claim 6, further comprising an intergate insulator 350 extending between the lower gate electrode Lower_GE1 and the first and second upper gate electrodes Upper_GE1, Upper_GE2,
wherein the lower gate contact Lower_CB1 extends through the intergate insulator 350.
In re claim 8, Xie discloses in figs. 1, 23-48, the integrated circuit device of Claim 1, wherein the upper transistor structure further comprises an upper channel region 354 (¶122), and the lower transistor structure further comprises a lower channel region 318 (¶115), and
a center of the upper channel region 354 in the second horizontal direction Y and a center of the lower channel region 318 in the second horizontal direction Y are offset from each other in the second horizontal direction Y.
In re claim 9, Xie discloses in figs. 1, 23-48, an integrated circuit device comprising:
first and second upper transistor structures (upper 425, 435) that are on a substrate 305 and are spaced apart from each other in a horizontal direction X (¶116, 136-137),
the first and second upper transistor structures comprising first and second upper gate electrodes, respectively (Upper_GE1, Upper_GE2, as shown in fig. 47 annotated below);
a lower transistor structure 440 (¶137) between the substrate 305 and the first and second upper transistor structures (upper 425, 435),
the lower transistor structure 440 comprising a lower gate electrode (Lower_GE1) that comprises a portion (e.g., a middle portion of the lower gate electrode surrounding the second bottom nano stack 318) not overlapped by the first and second upper gate electrodes;
an intergate insulator 350 extending between the lower gate electrode (Lower_GE1) and the first and second upper gate electrodes (Upper_GE1, Upper_GE2); and
a lower gate contact (Lower_CB1, as shown in fig. 47 annotated below) between the first and second upper gate electrodes (Upper_GE1, Upper_GE2),
the lower gate contact (Lower_CB1) extending through the intergate insulator 350 and is contact with the portion of the lower gate electrode (i.e., the middle portion of the lower gate electrode surrounding the second bottom nano stack 318).
In re claim 12, Xie discloses in figs. 1, 23-48, the integrated circuit device of Claim 9, wherein the first upper transistor structure further comprises a first upper channel region 354 (¶122), and the lower transistor structure further comprises a lower channel region 318 (¶115), and
a center of the first upper channel region 354 in the second horizontal direction Y and a center of the lower channel region 318 in the second horizontal direction Y are offset from each other in the second horizontal direction Y.
In re claim 13, Xie discloses in figs. 1, 23-48, the integrated circuit device of Claim 12, wherein a center of the first upper gate electrode (Upper_GE1) in the horizontal direction X and a center of the lower gate electrode (Lower_GE1) in the horizonal direction X are offset from each other in the horizontal direction X.
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Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5, 10-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xie, as applied to claims 1 and 9 above, respectively and further in view of Gardner et al. (US 20230056372 A1; hereinafter “Gardner”).
In re claim 5, Xie discloses in figs. 1, 23-48, the integrated circuit device of Claim 1, further comprising
an intergate insulator 350 extending between the lower gate electrode Lower_GE1 and the upper gate electrode Upper_GE1 (¶122),
wherein the lower gate electrode Lower_GE1 comprises a lower metal gate layer and a lower work function layer (“The gate 395 can be comprised of, for example, a gate dielectric liner, such as high-k dielectric like HfO.sub.2, ZrO.sub.2, HfL.sub.aO.sub.x, etc., and work function layers, such as TiN, TiAlC, TiC, etc., and conductive metal fills, like W”; ¶134).
Xie does not expressly disclose the lower work function layer extends between the intergate insulator and the lower metal gate layer.
In the same field of endeavor, Gardner discloses in figs. 1A-1C, an integrated circuit wherein a lower gate electrode 114 comprises a lower metal gate layer and a lower work function layer (Gardner discloses work function layer 114 can be made up of two or more layers of metals having different work functions; ¶54. Therefore, the inner metal layer of 114 has been interpreted as a lower metal gate layer and the outer metal layer of 114 has been interpreted as a lower work function layer),
the lower work function layer (i.e., the outer metal layer of 114) extends between an intergate insulator 137, 131 and the lower metal gate layer (i.e., the inner metal layer of 114).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to dispose the lower work function layer of Xie extending between the intergate insulator and the lower metal gate layer based on Gardner’s teachings in order to enable precise threshold voltage tuning and enhancing device performance.
In re claim 10, Xie discloses in figs. 1, 23-48, the integrated circuit device of Claim 9, wherein the lower gate electrode comprises a lower metal gate layer and a lower work function layer (“The gate 395 can be comprised of, for example, a gate dielectric liner, such as high-k dielectric like HfO.sub.2, ZrO.sub.2, HfL.sub.aO.sub.x, etc., and work function layers, such as TiN, TiAlC, TiC, etc., and conductive metal fills, like W”; ¶134).
Xie does not expressly disclose the lower work function layer extends between the intergate insulator and the lower metal gate layer.
In the same field of endeavor, Gardner discloses in figs. 1A-1C, an integrated circuit wherein a lower gate electrode 114 comprises a lower metal gate layer and a lower work function layer (Gardner discloses work function layer 114 can be made up of two or more layers of metals having different work functions; ¶54. Therefore, the inner metal layer of 114 has been interpreted as a lower metal gate layer and the outer metal layer of 114 has been interpreted as a lower work function layer),
the lower work function layer (i.e., the outer metal layer of 114) extends between an intergate insulator 137, 131 and the lower metal gate layer (i.e., the inner metal layer of 114).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to dispose the lower work function layer of Xie extending between the intergate insulator and the lower metal gate layer based on Gardner’s teachings to enable precise threshold voltage tuning and enhance device performance.
In re claim 11, Xie, as modified by Gardner, discloses the integrated circuit device of Claim 10, wherein the lower work function layer contacts (i.e., the outer metal layer of 114 in fig. 1C of Gardner) the intergate insulator (Xie: 350 in fig. 47).
Conclusion
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/NILUFA RAHIM/Primary Examiner, Art Unit 2893