DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-6, 8-13, and 15-20 have been amended.
Claims 1-20 have been examined.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 20 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 20 recites “the instruction.” There is insufficient antecedent basis for this limitation in the claims.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 8, and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US Publication No. 2020/0401408 by Burky et al. (hereinafter referred to as “Burky”).
Regarding claims 1, 8, and 15, taking claim 1 as representative, Burky discloses:
a computing device, comprising: resynchronization detection circuitry configured to detect, during an execution time of a first instruction, a resynchronization (Burky discloses, Figure 1, a computing device which discloses a processor, memory, and instructions. Burky also discloses, at ¶ [0078], detecting, which discloses circuitry do to so, a misprediction, which discloses a resynchronization, after a commit point, i.e., during execution time of an instruction.);
pointer regeneration circuitry configured to regenerate, in response to the detection, an instruction pointer at least in part by walking a queue (Burky discloses, at ¶ [0081], a UID pointer that points to an instruction to which execution can be rewound in response to detecting a misprediction. As disclosed at ¶ [0078], the recovery involves walking the entries of the register commit queue (RCQ) until the mispredict point is reached.); and
resynchronization circuitry configured to perform, during the execution time of the first instruction, the resynchronization by using the instruction pointer (Burky discloses, at ¶ [0081], restoring execution to the point indicated by the UID pointer before reaching another commit point, i.e., during the execution time of the instruction.),
wherein the instruction pointer identifies an address of a next instruction to be fetched (Burky discloses, at Figure 7 and related description, resuming execution from the mispredict point, which discloses the mispredict point is an instruction pointer that identifies the address of a next instruction to be fetched.).
Allowable Subject Matter
Claims 2-7, 9-14, and 16-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
On pages 9-10 of the response filed April 29, 2026 (“response”), the Applicant argues, “urky does not disclose regenerating an instruction pointer identifying an address of a next instruction to be fetched by walking a queue, but rather regenerating the speculative rename table (SRT) by walking a queue. As explained in Burky at [0072], "The SRT 74 represents the current speculative logical-to-physical register mappings which are active at the allocation point which represents the most recent uop which has been renamed speculatively." Thus, regenerating the SRT is not regenerating an instruction pointer identifying an address of a next instruction to be fetched. Burkey at [0078] states "A better approach for performance can be to try to recover the changes to the SRT 74 which were made due to the uops between the commit point and the mispredict point based on the RCQ 76. With this approach, when a misprediction is detected, any RCQ or ROB entries beyond the mispredict point can be flushed, but the entries corresponding to uops between the commit and the mispredict point are retained. The contents of the ART 72 could be copied to the SRT 74 when the misprediction is detected and then any RCQ entries which correspond to uops between the commit point and the mispredict point can be walked through to sequentially update the SRT 74 in response to each subsequent change of speculative register mapping which occurred when the uops between the commit point and the mispredict point were dispatched" (emphasis added). As noted above, regenerating the SRT is not regenerating an instruction pointer identifying an address of a next instruction to be fetched. Burky at [0081] states that "Each checkpoint 82 may be associated with a set of checkpoint state information 84 indicating properties of that checkpoint. For example the checkpoint state information 84 may include a valid field 86 which indicates whether the corresponding checkpoint is valid; a UID or ROB pointer field 88 which represents either the UID of the uop at the point of execution for which the checkpoint was captured, or a pointer to the entry of the reorder buffer 50 corresponding to that uop; a RCQ pointer 90 which points to the location in the RCQ 76 corresponding to the point at which the checkpoint was taken" (emphasis added). Neither the ROB pointer nor the RCQ pointer described by Burky is an instruction pointer identifying an address of a next instruction to be fetched. Thus, Burky does not disclose at least "circuitry configured to regenerate, in response to the detection, an instruction pointer at least in part by walking a queue" and "wherein the instruction pointer is a pointer identifying a memory address of a next instruction to be fetched" as recited in amended claim 1.”
Though fully considered, the Examiner respectfully disagrees. Burky discloses recovering from misprediction. See, e.g., Figure 3 and related description. This involves resynchronizing from a point at which execution was known to be correct, e.g., one of the checkpoints, until the point at which the misprediction occurred. Id. Once the instructions between the checkpoint and the mispredict point are recovered, execution resumes at the point indicated by the mispredict pointer. The Examiner maintains that this discloses the claimed regenerating the instruction pointer and that the instruction pointer points to the next instruction to be fetched. Accordingly, the Applicant’s arguments are deemed unpersuasive.
Conclusion
THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAWN DOMAN whose telephone number is (571)270-5677. The examiner can normally be reached on Monday through Friday 8:30am-6pm Eastern Time.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHAWN DOMAN/
Primary Examiner, Art Unit 2183
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