DETAILED ACTION
This action is responsive to the application No. 18/475,566 filed on September 27, 2023.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgment
The amendment filed on 06/11/2026 responding to the Office action mailed on 03/11/2026, has been entered. The present Office action is made with all the suggested amendments being fully considered. Claim 7 is withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a non-elected species, there being no allowable generic or linking claim. Accordingly, pending in this Office action are claims 1-20.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-6, 8, 9, and 11-19 are rejected under 35 U.S.C. 103 as being unpatentable over Jo (US 2021/0407890) in view of Liu (US 2025/0070062).
Regarding Claim 1, Jo (see, e.g., Figs. 1-3), teaches a semiconductor device, comprising:
a first connection 161 (see, e.g., par. 0039);
a substrate 201 comprising a first side (i.e., top side) and a second side (i.e., bottom side), the first connection 161 being coupled to the first side (see, e.g., par. 0026);
a grid 150 coupled to the second side (see, e.g., pars. 0043);
a second connection 175 coupled to the grid 150 (see, e.g., par. 0051);
a first via 120 coupled to the first connection 161 and the grid 150 (see, e.g., par. 0021); and
a second via 120 coupled to the first connection 161 and the second connection 175, a first distance 121 between the first via 120 and the second via 120 being less than 20 µm (see, e.g., par. 0031).
Jo is silent with respect to the claim limitation that the grid comprises a network of interlinking conductive lines or tracks.
Liu (see, e.g., Fig. 2), on the other hand, teaches that the grid 220 comprises a network of interlinking conductive lines or tracks 222/223, increasing a surface area of the first conductive connection pad 220, and further increasing a heat dissipation area of the semiconductor interconnection structure. Furthermore, the mesh structure of the first conductive connection pad 220 can further improve deformation resistance of the conductive pillar array, thereby improving support performance of the semiconductor interconnection structure (see, e.g., par. 0026).
It would have been obvious to one of ordinary skill in the art at the time of filing to include in Jo’s device, the grid comprising a network of interlinking conductive lines or tracks, as taught by Liu, to increase a surface area of the first conductive connection pad, and further increase a heat dissipation area of the semiconductor interconnection structure. Furthermore, the mesh structure of the first conductive connection pad can further improve deformation resistance of the conductive pillar array, thereby improving support performance of the semiconductor interconnection structure.
Regarding Claim 3, Jo and Liu teach all aspects of claim 1. They do not specify that the first connection comprises a power grid strap.
However, the limitation that “the first connection comprises a power grid strap” does not appear to structurally limit the claim as it is directed to (i) a manner of operating a device or (ii) function, property or characteristic of the semiconductor device.
A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim. Exparte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987).
According to Section 2114 of the MPEP, "While features of an apparatus may berecited either structurally or functionally, claims directed to an apparatus must bedistinguished from the prior art in terms of structure rather than function. In reSchreiber, 128 F.3d 1473, 1477-78, 44 USPQ2d 1429,1431-32 (Fed. Cir. 1997) (Theabsence of a disclosure in a prior art reference relating to function did not defeat theBoard's finding of anticipation of claimed apparatus because the limitations at issuewere found to be inherent in the prior art reference); see also In re Swinehart, 439 F.2d210,212-13, 169 USPQ 226, 228-29 (CCPA 1971); In re Danly, 263 F.2d 844, 847, 120USPQ 528,531 (CCPA 1959). "[A]pparatus claims cover what a device is, not what adevice does." Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15USPQ2d 1525, 1528 (Fed. Cir. 1990) (emphasis in original)".
Construing the limitation of claim 3 as (i) a manner of operating the device,Jo/Liu disclose all the structural limitations as required by claim 3, including the first connection 161, thus a recitation with respect to the manner in which the claimed device is intended to be employed, such that the first connection comprises a power grid strap, does not differentiate the claimed device from the prior art device.
Regarding Claim 4, Jo and Liu teach all aspects of claim 1. Jo (see, e.g., Figs. 1-3), teaches that the second connection 175 comprises a solder bump (see, e.g., par. 0051).
Regarding Claim 5, Jo and Liu teach all aspects of claim 1. Jo (see, e.g., Figs. 1-3), teaches that the first via 120 comprises a through silicon via (see, e.g., par. 0021).
Regarding Claim 6, Jo and Liu teach all aspects of claim 1. Jo (see, e.g., Figs. 1-3), teaches further comprising a third connection 176 coupled to the grid 150. They are silent with respect to the claim limitation that a distance between the second connection 30 and the third connection is 30 between 100µm to 200µm.
However, this claim limitation is merely considered a change in the distance between the second connection 30 and the third connection 30 in Jo’s/Liu’s device. The specific claimed distance, absent any criticality, is only considered to be an obvious modification of the distance between second connection 30 and the third connection 30 in Jo’s/Liu’s device, as the courts have held that changes distance without any criticality, are within the level of skill in the art. According to the courts, a particular distance is nothing more than one among numerous distances that a person having ordinary skill in the art will find obvious to provide using routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Accordingly, since the applicant has not established the criticality (see next paragraph below) of the claimed distance, it would have been obvious to one of ordinary skill in the art at the time of filing, to have the claimed distance between the second connection and the third connection in Liu’s/Jo’s device.
CRITICALITY
The specification contains no disclosure of either the critical nature of the claimed distance or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen distance or upon another variable recited in a claim, the applicant must show that the chosen distance is critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Regarding Claim 8, Jo (see, e.g., Figs. 1-3), teaches a semiconductor device comprising:
a first connection 161 (see, e.g., par. 0039);
a substrate 110 comprising a first opening and a second opening, the substrate 110 comprising a first side (i.e., top side) and a second side (i.e., bottom side), the first connection 1610 being coupled to the first side (see, e.g., par. 0026);
a grid 150 coupled to the second side (see, e.g., par. 0043);
a second connection 175 coupled to the grid 150 (see, e.g., par. 0051;
a first via 120 coupled to the first connection 161 and the grid 150, the first via 120 comprising a first portion positioned in the first opening (see, e.g., par. 0021); and
a second via 120 coupled to the first connection 161 and the grid 150, the second via 120 comprising a second portion positioned in the second opening, a first distance between the first via and the second via is less than 20µm (see, e.g., par. 0031).
Jo is silent with respect to the claim limitation that the grid comprises a network of interlinking conductive lines or tracks.
Liu (see, e.g., Fig. 2), on the other hand, teaches that the grid 220 comprises a network of interlinking conductive lines or tracks 222/223, increasing a surface area of the first conductive connection pad 220, and further increasing a heat dissipation area of the semiconductor interconnection structure. Furthermore, the mesh structure of the first conductive connection pad 220 can further improve deformation resistance of the conductive pillar array, thereby improving support performance of the semiconductor interconnection structure (see, e.g., par. 0026).
It would have been obvious to one of ordinary skill in the art at the time of filing to include in Jo’s device, the grid comprising a network of interlinking conductive lines or tracks, as taught by Liu, to increase a surface area of the first conductive connection pad, and further increase a heat dissipation area of the semiconductor interconnection structure. Furthermore, the mesh structure of the first conductive connection pad can further improve deformation resistance of the conductive pillar array, thereby improving support performance of the semiconductor interconnection structure.
Regarding Claim 9, Jo and Liu teach all aspects of claim 8. Jo (see, e.g., Figs. 1-3), teaches further comprising a third via 120 and a plurality of vias 120, the plurality of vias 120 being positioned between the third via 120 and the second via 120, a second distance between the third via 120 and the second via 120 being less than 20µm (see, e.g., Jo, Fig. 1, par. 0031).
Regarding Claim 11, Jo and Liu teach all aspects of claim 8. Jo (see, e.g., Figs. 1-3), teaches that the first via 120 comprises a through silicon via (see, e.g., par. 0021).
Regarding Claim 12, Jo (see, e.g., Figs. 1-3), teaches a semiconductor device comprising:
a substrate 110 comprising a first side (i.e., top side) and a second side (i.e., bottom side) (see, e.g., par. 0026);
a first connection 161 coupled to the first side of the substrate 110 (see, e.g., par. 0039);
a grid 150 coupled to the second side of the substrate 110, the grid 150 comprising a first region (see, e.g., par. 0043); and
a first via 120 coupled between the first connection 161 and the first region of the grid 150, the first via 120 comprising a first portion positioned in a first opening of the substrate 110 (see, e.g., par. 0021).
Jo is silent with respect to the claim limitation that the grid comprises a network of interlinking conductive lines or tracks.
Liu (see, e.g., Fig. 2), on the other hand, teaches that the grid 220 comprises a network of interlinking conductive lines or tracks 222/223, increasing a surface area of the first conductive connection pad 220, and further increasing a heat dissipation area of the semiconductor interconnection structure. Furthermore, the mesh structure of the first conductive connection pad 220 can further improve deformation resistance of the conductive pillar array, thereby improving support performance of the semiconductor interconnection structure (see, e.g., par. 0026).
It would have been obvious to one of ordinary skill in the art at the time of filing to include in Jo’s device, the grid comprising a network of interlinking conductive lines or tracks, as taught by Liu, to increase a surface area of the first conductive connection pad, and further increase a heat dissipation area of the semiconductor interconnection structure. Furthermore, the mesh structure of the first conductive connection pad can further improve deformation resistance of the conductive pillar array, thereby improving support performance of the semiconductor interconnection structure.
Regarding Claim 13, Jo and Liu teach all aspects of claim 12. Jo (see, e.g., Figs. 1-3), teaches further comprising a second connection 175 coupled to the first region of the grid 150 (see, e.g., par. 0051).
Regarding Claim 14, Jo and Liu teach all aspects of claim 13. Jo (see, e.g., Figs. 1-3), teaches that the second connection 175 comprises a solder bump (see, e.g., par. 0051).
Regarding Claim 15, Jo and Liu teach all aspects of claim 13. Jo (see, e.g., Figs. 1-3), teaches that the grid 150 further comprises a second region, the second region is not coupled to the second connection 175.
Regarding Claim 16, Jo and Liu teach all aspects of claim 15. Jo (see, e.g., Figs. 1-3), teaches further comprising a second via 120 coupled between the first connection 161 and the second region of the grid 150, the second via 120 comprising a second portion positioned in a second opening of the substrate 110.
Regarding Claim 17, Jo and Liu teach all aspects of claim 16. Jo (see, e.g., Figs. 1-3), teaches that a first distance 121 between the first via 120 and the second via 120 is less than 20µm (see, e.g., par. 0031).
Regarding Claim 18, Jo and Liu teach all aspects of claim 12. They do not specify that the first connection comprises a power grid strap.
However, the limitation that “the first connection comprises a power grid strap” does not appear to structurally limit the claim as it is directed to (i) a manner of operating a device or (ii) function, property or characteristic of the semiconductor device.
A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim. Exparte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987).
According to Section 2114 of the MPEP, "While features of an apparatus may berecited either structurally or functionally, claims directed to an apparatus must bedistinguished from the prior art in terms of structure rather than function. In reSchreiber, 128 F.3d 1473, 1477-78, 44 USPQ2d 1429,1431-32 (Fed. Cir. 1997) (Theabsence of a disclosure in a prior art reference relating to function did not defeat theBoard's finding of anticipation of claimed apparatus because the limitations at issuewere found to be inherent in the prior art reference); see also In re Swinehart, 439 F.2d210,212-13, 169 USPQ 226, 228-29 (CCPA 1971); In re Danly, 263 F.2d 844, 847, 120USPQ 528,531 (CCPA 1959). "[A]pparatus claims cover what a device is, not what adevice does." Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15USPQ2d 1525, 1528 (Fed. Cir. 1990) (emphasis in original)".
Construing the limitation of claim 18 as (i) a manner of operating the device,Jo/Liu disclose all the structural limitations as required by claim 18, including the first connection 161, thus a recitation with respect to the manner in which the claimed device is intended to be employed, such that the first connection comprises a power grid strap, does not differentiate the claimed device from the prior art device.
Regarding Claim 19, Jo and Liu teach all aspects of claim 12. Jo (see, e.g., Figs. 1-3), teaches that the first via 120 is configured to transmit electrical power between the first side and the second side (see, e.g., par. 0026).
Claims 2, 10, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Jo (US 2021/0407890) in view of Liu (US 2025/0070062) and further in view of Yilmaz (US 2007/0235886).
Regarding Claims 2, 10, and 20, Jo and Liu teach all aspects of claims 1, 8, and 19. They are silent with respect to the claim limitation that the first via is characterized by a maximum current of less than 40mA.
Yilmaz, on the other hand, teaches that the size and quantity of the vias can also be altered to meet electrical current demands (see, e.g., par. 0052).
However, this claim limitation can be achieved by merely changing the size of the via in Jo’s/Liu’s device. The specific claimed maximum current being less than 40mA, absent any criticality, can be achieved by the obvious modification of changing the size of the via in Jo’s/Liu’s device, as the courts have held that changes in size without any criticality, are within the level of skill in the art. According to the courts, a particular size is nothing more than one among numerous sizes that a person having ordinary skill in the art will find obvious to provide using routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Accordingly, since the applicant has not established the criticality (see next paragraph below) of the claimed maximum current being less than 40mA, it would have been obvious to one of ordinary skill in the art at the time of filing, to have a via characterized by a maximum current of less than 40mA in Jo’s/Liu’s device.
CRITICALITY
The specification contains no disclosure of either the critical nature of the claimed maximum current being less than 40mA or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen size or upon another variable recited in a claim, the applicant must show that the chosen size is critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Response to Arguments
Applicant’s arguments filed on 06/11/2026 with respect to the rejection of claims 1, 8, and 12 have been fully considered but are moot in view of the new grounds of rejection.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Nelson Garces whose telephone number is (571) 272-8249. The examiner can normally be reached on Mon-Fri 9:00 AM-5:30 PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Wael Fahmy can be reached on (571) 272-1705.
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/Nelson Garces/Primary Examiner, Art Unit 2814
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