Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Information Disclosure Statement
Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-16 are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (US Pub # 2019/0312196).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding independent claim 1, Choi et al. teach a synapse memory system, comprising: an analog memory, comprising: a free layer, the free layer including fixed regions disposed at end portions thereof and a data region interposed between the fixed regions (see Fig. 1-7, 9-15 and paragraph 0004-0008, 0066-0072, 0075-0082, 0085-0095, 0099-0109, 0113-0117, 0126-0136, 0146-0149, 0151-0154, 0157-0164, 0182-0188, Synapse 304, free layer 502, data region includes magnetic storage layer); and a plurality of pinning layers disposed on each respective fixed region, wherein excitation of the fixed regions by the pinning layers induces opposed magnetic fields in each respective fixed region, the opposed magnetic fields defining a domain wall at an inflection point of the opposed magnetic fields of the fixed regions (see Fig. 1-7, 9-15 and paragraph 0004-0008, 0066-0072, 0075-0082, 0085-0095, 0099-0109, 0113-0117, 0126-0136, 0146-0149, 0151-0154, 0157-0164, 0182-0188, Pinning sites includes pinning layer, write current / excitation control magnetic field of free layer / fixed region, applying current opposite to first direction move domain wall 1050 due to oppose magnetic field).
Even though Choi et al. teach magnetic storage layer but silent exclusively about data region. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Choi et al. where magnetic storage layer basically store data using fixed magnetization for the reference layer which would be called data region in order to provide reversible write / store data operation due to prevention of domain wall migration into stabilized portion of free layer (see paragraph 0151).
Regarding claim 2, Choi et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Choi et al. further teach, wherein a length of the analog memory is greater than a width of the analog memory, the length and width of the analog memory defining an aspect ratio (see Fig. 1-7, 9-15 and paragraph 0004-0008, 0066-0072, 0075-0082, 0085-0095, 0099-0109, 0113-0117, 0126-0136, 0146-0149, 0151-0154, 0157-0164).
Regarding claim 3, Choi et al. teach all claimed subject matter as applied in prior rejection of claim 2 on which this claim depends.
Choi et al. further teach, wherein the aspect ratio of the analog memory is large (see Fig. 1-7, 9-15 and paragraph 0004-0008, 0066-0072, 0075-0082, 0085-0095, 0099-0109, 0113-0117, 0126-0136, 0146-0149, 0151-0154).
Regarding claim 4, Choi et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Choi et al. further teach, wherein the analog memory is incorporated within a synapse memory cell (see Fig. 1-7, 9-15 and paragraph 0004-0008, 0066-0072, 0075-0082, 0085-0095, 0099-0109, 0113-0117, 0126-0136, 0146-0149, 0151-0154, 0157-0158).
Regarding claim 5, Choi et al. teach all claimed subject matter as applied in prior rejection of claim 4 on which this claim depends.
Choi et al. further teach, wherein dynamic ranges of a plurality of analog memories are combined to obtain a dynamic range of the synapse memory cell as a whole (see Fig. 1-7, 9-15 and paragraph 0004-0008, 0066-0072, 0075-0082, 0085-0095, 0099-0109, 0113-0117, 0126-0136, 0146-0149, 0151-0154, 0157-0160).
Regarding claim 6, Choi et al. teach all claimed subject matter as applied in prior rejection of claim 4 on which this claim depends.
Choi et al. further teach, wherein an aspect ratio of each synapse memory cell is smaller than an aspect ratio of each analog memory (see Fig. 1-7, 9-15 and paragraph 0004-0008, 0066-0072, 0075-0082, 0085-0095, 0099-0109, 0113-0117, 0126-0136, 0146-0149).
Regarding claim 7, Choi et al. teach all claimed subject matter as applied in prior rejection of claim 4 on which this claim depends.
Choi et al. further teach, wherein an aspect ratio of each synapse memory cell is almost 1:1 (see Fig. 1-7, 9-15 and paragraph 0004-0008, 0066-0072, 0075-0082, 0085-0095, 0099-0109, 0113-0117, 0126-0136, 0146-0149, 0151-0154, 0157).
Regarding claim 8, Choi et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Choi et al. further teach, wherein each analog memory is a non-volatile random access memory (NVRAM) (see Fig. 1-7, 9-15 and paragraph 0004-0008, 0066-0072, 0075-0082, 0085-0095, 0099-0109, 0113-0117, 0126-0136, 0146-0149, 0151-0153).
Regarding independent claim 9, Choi et al. teach an analog memory for use in a synapse memory cell, comprising: a free layer, the free layer including fixed regions disposed at end portions thereof and a data region interposed between the fixed regions (see Fig. 1-7, 9-15 and paragraph 0004-0008, 0066-0072, 0075-0082, 0085-0095, 0099-0109, 0113-0117, 0126-0136, 0146-0149, 0151-0154, 0157-0164, 0182-0188, Synapse 304, free layer 502, data region includes magnetic storage layer); and a plurality of pinning layers disposed on each respective fixed region, wherein excitation of the fixed regions by the pinning layers induces opposed magnetic fields in each respective fixed region, the opposed magnetic fields defining a domain wall at an inflection point of the opposed magnetic fields of the fixed regions (see Fig. 1-7, 9-15 and paragraph 0004-0008, 0066-0072, 0075-0082, 0085-0095, 0099-0109, 0113-0117, 0126-0136, 0146-0149, 0151-0154, 0157-0164, 0182-0188, Pinning sites includes pinning layer, write current / excitation control magnetic field of free layer / fixed region, applying current opposite to first direction move domain wall 1050 due to oppose magnetic field).
Even though Choi et al. teach magnetic storage layer but silent exclusively about data region. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Choi et al. where magnetic storage layer basically store data using fixed magnetization for the reference layer which would be called data region in order to provide reversible write / store data operation due to prevention of domain wall migration into stabilized portion of free layer (see paragraph 0151).
Regarding claim 10, Choi et al. teach all claimed subject matter as applied in prior rejection of claim 9 on which this claim depends.
Choi et al. further teach, wherein a length of the analog memory is greater than a width of the analog memory, the length and width of the analog memory defining an aspect ratio (see Fig. 1-7, 9-15 and paragraph 0004-0008, 0066-0072, 0075-0082, 0085-0095, 0099-0109, 0113-0117, 0126-0136, 0146-0149, 0151-0154, 0157-0164).
Regarding claim 11, Choi et al. teach all claimed subject matter as applied in prior rejection of claim 10 on which this claim depends.
Choi et al. further teach, wherein the aspect ratio of the analog memory is large (see Fig. 1-7, 9-15 and paragraph 0004-0008, 0066-0072, 0075-0082, 0085-0095, 0099-0109, 0113-0117, 0126-0136, 0146-0149, 0151-0154).
Regarding claim 12, Choi et al. teach all claimed subject matter as applied in prior rejection of claim 9 on which this claim depends.
Choi et al. further teach, wherein the analog memory is incorporated within a synapse memory cell (see Fig. 1-7, 9-15 and paragraph 0004-0008, 0066-0072, 0075-0082, 0085-0095, 0099-0109, 0113-0117, 0126-0136, 0146-0149, 0151-0152).
Regarding claim 13, Choi et al. teach all claimed subject matter as applied in prior rejection of claim 12 on which this claim depends.
Choi et al. further teach, wherein dynamic ranges of a plurality of analog memories are combined to obtain a dynamic range of the synapse memory cell as a whole (see Fig. 1-7, 9-15 and paragraph 0004-0008, 0066-0072, 0075-0082, 0085-0095, 0099-0109, 0113-0117, 0126-0136, 0146-0149, 0151-0154, 0157-0160).
Regarding claim 14, Choi et al. teach all claimed subject matter as applied in prior rejection of claim 12 on which this claim depends.
Choi et al. further teach, wherein an aspect ratio of the synapse memory cell is smaller than an aspect ratio of the analog memory (see Fig. 1-7, 9-15 and paragraph 0004-0008, 0066-0072, 0075-0082, 0085-0095, 0099-0109, 0113-0117, 0126-0136, 0146-0149, 0151-0154).
Regarding claim 15, Choi et al. teach all claimed subject matter as applied in prior rejection of claim 12 on which this claim depends.
Choi et al. further teach wherein an aspect ratio of the synapse memory cell is almost 1:1 (see Fig. 1-7, 9-15 and paragraph 0004-0008, 0066-0072, 0075-0082, 0085-0095, 0099-0109, 0113-0117, 0126-0136, 0146-0149).
Regarding claim 16, Choi et al. teach all claimed subject matter as applied in prior rejection of claim 9 on which this claim depends.
Choi et al. further teach, wherein each analog memory is a non-volatile random access memory (NVRAM) (see Fig. 1-7, 9-15 and paragraph 0004-0008, 0066-0072, 0075-0082, 0085-0095, 0099-0109, 0113-0117, 0126-0136, 0146-0149, 0151-0154, 0157-0158).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See attachment.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED A BASHAR whose telephone number is 469-295-9277. The examiner can normally be reached on 9am-5pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard T Elms can be reached on 5712721869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOHAMMED A BASHAR/Primary Examiner, Art Unit 2824
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