DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 8-10, 12, 21-23 are rejected under 35 U.S.C. 102(a)(a) and 102(a)(2) as being anticipated by Chen et al. (US 2022/0165730) hereinafter “Chen”.
Regarding claim 8, Fig. 28A of Chen teaches a complementary field-effect transistor (CFET) device (Paragraph 0072) comprising: a substrate; a fin (Item 202);a first plurality of channel regions (Items 106b) disposed vertically over the fin (Item 202);a second plurality of channel regions (Item 106d) disposed vertically over the first plurality of channel regions (Items 106b); an isolation structure (Item 2602) between the first plurality of channel regions (Items 106b) and the second plurality of channel regions (Items 106d); a first etch stop layer (ESL) (Item 106c under Item 2602; See Examiner’s Note) on a lower surface of the isolation structure (Item 2602) facing the fin (Item 202); a second ESL (Item 106c over Item 2602; See Examiner’s Note) on an upper surface of the isolation structure (Item 2602) distal from the fin (Item 202), wherein the first ESL (Lower Item 106c), the second ESL (Upper Item 106c), the first plurality of channel regions (Items 106b), and the second plurality of channel regions (Items 106d) are a same semiconductor material (Paragraph 0026 where Item 106 is SiGe); first source/drain regions (Item 1602) at opposing ends of the first plurality of channel regions; second source/drain regions (Not labeled in Fig. 28A; See Fig. 22, Item 2102) at opposing ends of the second plurality of channel regions; dielectric structures (Combination of Items 1902 and 1802) at opposing ends of the isolation structure (Item 2602) and disposed vertically between the first source/drain regions (Item 1602) and the second source/drain regions (Item 2102); a first gate structure (Item 2502) around the first plurality of channel regions (Items 106b); and a second gate structure (Item 2702) around the second plurality of channel regions (Items 106d).
Examiner’s Note: The Examiner notes that even though the layers in Chen indicated by the Examiner as first and second ESL layers are not explicitly labeled as ESL layers, the layers are capable of acting as ESL layers. This is all that is required by the claim as the claim is directed to a device and not a method such that no active etching is taking place.
Regarding claim 9, Fig. 28A of Chen further teaches where the first ESL (Lower Item 106c) and the second ESL (Item Upper Item 106c) are thinner than the first plurality of channel regions (Items 106b) and the second plurality of channel regions (Items 106d).
Regarding claim 10, Fig. 28A of Chen further teaches first inner spacers (Items 1504 surrounding Items 2502) disposed laterally between the first gate structure (Item 2502) and the first source/drain regions (Items 1602); and second inner spacers (Items 1504 surrounding Items 2702) disposed laterally between the second gate structures (Items 2702) and the second source/drain regions (Item 2102).
Regarding claim 12, Fig. 28A of Chen further teaches where an upper surface of the dielectric structures (Combination of Items 1902 and 1802) distal from the fin is closer to the fin than a lowermost surface of the second plurality of channel regions (Item 106d) facing the fin, wherein a lower surface of the dielectric structures (Combination of Items 1902 and 1802) facing the fin is further from the fin than an uppermost surface of the first plurality of channel regions (Item 106b) distal from the fin.
Regarding claim 21, Fig. 28A of Chen teaches a complementary field-effect transistor (CFET) device (Paragraph 0072) comprising: a substrate; a fin (Item 202) protruding above the substrate; first channel regions (Items 106b) vertically stacked over the fin (Item 202); second channel regions (Item 106d) vertically stacked over the first channel regions (Items 106b); an isolation structure (Combination of Items 2602 and 106c) between the first channel regions (Items 106b) and the second channel regions (Items 106d); a first gate structure (Item 2502) around the first channel regions (Items 106b); a second gate structure (Item 2702) around the second channel regions (Items 106d); first source/drain regions (Item 1602) at opposing ends of the first channel regions; second source/drain regions (Not labeled in Fig. 28A; See Fig. 22, Item 2102) at opposing ends of the second channel regions; and dielectric structures (Combination of Items 1902 and 1802) between the first source/drain regions (Item 1602) and the second source/drain regions (Item 2102), where the isolation structure (Combination of Items 2602 and 106c) is disposed laterally between the dielectric structures (Combination of Items 1902 and 1802), where upper surfaces of the dielectric structures distal from the substrate extend further from the substrate than an upper surface of the isolation structure distal from the substrate, where lower surfaces of the dielectric structures facing the substrate extend closer to the substrate than a lower surface of the isolation structure facing the substrate.
Regarding claim 22, Fig. 28A of Chen further teaches first inner spacers (Item 1504) disposed laterally between the first gate structure (Item 2502) and the first source/drain regions (Item 1602), wherein an uppermost first inner spacer of the first inner spacers is in contact with the isolation structure (Combination of Items 2602 and 106c), wherein a lower surface of the uppermost first inner spacer extends closer to the substrate than the lower surfaces of the dielectric structures (Combination of Items 1902 and 1802); and second inner spacers (Items 1504) disposed laterally between the second gate structure (Item 2702) and the second source/drain regions (Item 2102), wherein a lowermost second inner spacer of the second inner spacers is in contact with the isolation structure (Combination of Items 2602 and 106c), wherein an upper surface of the lowermost second inner spacer extends further from the substrate than the upper surfaces of the dielectric structures (Combination of Items 1902 and 1802).
Examiner’s Note: The Examiner notes that even though the layers in Chen indicated by the Examiner as first and second ESL layers are not explicitly labeled as ESL layers, the layers are capable of acting as ESL layers. This is all that is required by the claim as the claim is directed to a device and not a method such that no active etching is taking place.
Regarding claim 21, under an alternate interpretation of Chen, Fig. 28A of Chen teaches a complementary field-effect transistor (CFET) device (Paragraph 0072) comprising: a substrate; a fin (Item 202) protruding above the substrate; first channel regions (Items 106b) vertically stacked over the fin (Item 202); second channel regions (Item 106d) vertically stacked over the first channel regions (Items 106b); an isolation structure (Combination of Items 2602 and 2404 and 2403) between the first channel regions (Items 106b) and the second channel regions (Items 106d); a first gate structure (Item 2502) around the first channel regions (Items 106b); a second gate structure (Item 2702) around the second channel regions (Items 106d); first source/drain regions (Item 1602) at opposing ends of the first channel regions; second source/drain regions (Not labeled in Fig. 28A; See Fig. 22, Item 2102) at opposing ends of the second channel regions; and dielectric structures (Combination of Items 1902 and 1802) between the first source/drain regions (Item 1602) and the second source/drain regions (Item 2102), where the isolation structure (Combination of Items 2602 and 2404 and 2403) is disposed laterally between the dielectric structures (Combination of Items 1902 and 1802), where upper surfaces of the dielectric structures distal from the substrate extend further from the substrate than an upper surface of the isolation structure distal from the substrate, where lower surfaces of the dielectric structures facing the substrate extend closer to the substrate than a lower surface of the isolation structure facing the substrate.
Regarding claim 23, under the alternate interpretation of Chen, Fig. 28A of Chen further teaches a first etch stop layer (ESL) (Item 106c under Item 2602; See Examiner’s Note) extending along a lower surface of the isolation structure (Item 2602) facing the substrate; and a second ESL (Item 106c over Item 2602; See Examiner’s Note) extending along an upper surface of the isolation structure (Item 2602) distal from the substrate, wherein the first channel regions (Items 106b), the second channel regions (Items 106d), the first ESL (Lower Item 106c),and the second ESL (Upper Item 106c) have a same material composition (Paragraph 0026 where Item 106 is SiGe), where the first ESL and the second ESL are thinner than the first channel regions (Items 106b) and the second channel regions (Items 106d).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2022/0165730) hereinafter “Chen” in view of Xie et al. (US 2021/0265348) hereinafter “Xie”.
Regarding claim 11, Fig. 28A of Chen further teaches where the dielectric structures (Combination of Items 1902 and 1802) contact and extend along sidewalls of the first ESL (Lower Item 106c), sidewalls of the second ESL (Upper 106c), sidewalls of uppermost ones of the first inner spacers (Item 1504), and sidewalls of lowermost ones of the second inner spacers (Item 1504).
Chen does not explicitly teach where the dielectric structures contact and extend along sidewalls of the isolation structure.
Fig. 5 of Xie teaches where a dielectric structure (Item 402) vertically separating first and second source/drain regions contacts and extends along sidewalls of an isolation structure (Item 202) vertically separating first and second channel regions.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the dielectric structures contact and extend along sidewalls of the isolation structure because this configuration does not require additional deposition of inner spacers while the dielectric structures electrically isolate first and second channel region stacks (Xie Paragraph 0038).
Claims 13, 14, 16, 17, 20, 24 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2022/0165730) hereinafter “Chen” in view of Frougier et al. (US 2023/0086633) hereinafter “Frougier”.
Regarding claim 13, Chen teaches all of the elements of the claimed invention as stated above except a first interfacial layer embedded in the first ESL between the isolation structure and the first gate structure; and a second interfacial layer embedded in the second ESL between the isolation structure and the second gate structure, wherein the first interfacial layer and the second interfacial layer are an oxide of the semiconductor material of the first ESL.
Fig. 12B of Frougier teaches thin interfacial layers (Paragraph 0075 where a thin interfacial layer is grown during a preclean step of the channel regions) embedded in top and bottom surface of channel regions.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have a first interfacial layer embedded in the first ESL between the isolation structure and the first gate structure; and a second interfacial layer embedded in the second ESL between the isolation structure and the second gate structure, wherein the first interfacial layer and the second interfacial layer are an oxide of the semiconductor material of the first ESL because the interfacial layers are formed during a preclean step such that high-k dielectric material can be better grown on the semiconductor layers (Frougier Paragraph 0075).
Regarding claim 14, Chen teaches all of the elements of the claimed invention as stated above except wherein end portions of the isolation structure are in contact with the dielectric structures, wherein a middle portion of the isolation structure is disposed laterally between the end portions of the isolation structure, wherein a first portion of the first ESL extends along the end portions of the isolation structure, and a second portion of the first ESL extends along the middle portion of the isolation structure, wherein the first portion of the first ESL is thicker than the second portion of the first ESL.
Frougier further teaches where, during a preclean step, the channel layers are indented in the middle portion such that a middle portion of the channel region is thinner than end portions of the channel region (Paragraph 0075).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have end portions of the isolation structure are in contact with the dielectric structures, wherein a middle portion of the isolation structure is disposed laterally between the end portions of the isolation structure, wherein a first portion of the first ESL extends along the end portions of the isolation structure, and a second portion of the first ESL extends along the middle portion of the isolation structure, wherein the first portion of the first ESL is thicker than the second portion of the first ESL because the shape of the semiconductor layers, having a thinner middle portion than end portions, is formed during a preclean step such that high-k dielectric material can be better grown on the semiconductor layers (Frougier Paragraph 0075).
Regarding claim 16, Chen teaches all of the elements of the claimed invention as stated above except where in a cross section along a longitudinal direction of the first plurality of channel regions, the first interfacial layer has a smaller thickness than the first ESL, or the second interfacial layer has a smaller thickness than the second ESL.
Frougier further teaches where, during a preclean step, the channel layers are indented in the middle portion such that a middle portion of the channel region is thinner than end portions of the channel region (Paragraph 0075).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have, in a cross section along a longitudinal direction of the first plurality of channel regions, the first interfacial layer has a smaller thickness than the first ESL, or the second interfacial layer has a smaller thickness than the second ESL because the shape of the semiconductor layers, having a thinner middle portion than end portions, is formed during a preclean step such that high-k dielectric material can be better grown on the semiconductor layers (Frougier Paragraph 0075).
Regarding claim 17, Fig. 28A of Chen teaches a complementary field-effect transistor (CFET) device (Paragraph 0072) comprising: a fin (Item 202) protruding above a substrate; first channel regions (Items 106b) vertically stacked over the fin (Item 202); second channel regions (Item 106d) vertically stacked over the first channel regions (Items 106b); an isolation structure (Item 2602) between the first channel regions (Items 106b) and the second channel regions (Items 106d); a first gate structure (Item 2502) around the first channel regions (Items 106b); a second gate structure (Item 2702) around the second channel regions (Items 106d); a first etch stop layer (ESL) (Item 106c under Item 2602; See Examiner’s Note) extending along a lower surface of the isolation structure (Item 2602) facing the substrate; a second ESL (Item 106c over Item 2602; See Examiner’s Note) extending along an upper surface of the isolation structure (Item 2602) distal from the substrate (Item 202), wherein the first channel regions (Items 106b), the second channel regions (Items 106d), the first ESL (Lower Item 106c), and the second ESL (Upper Item 106c) are a semiconductor material (Paragraph 0026 where Item 106 is SiGe); first source/drain regions (Item 1602) at opposing ends of the first channel regions; second source/drain regions (Not labeled in Fig. 28A; See Fig. 22, Item 2102) at opposing ends of the second channel regions; and dielectric structures (Combination of Items 1902 and 1802) at opposing ends of the isolation structure (Item 2602), where the dielectric structures (Combination of Items 1902 and 1802) separate the first source/drain regions (Item 1602) and the second source/drain regions (Item 2102).
Chen does not teach a first interfacial layer embedded in the first ESL between the isolation structure and the first gate structure nor a second interfacial layer embedded in the second ESL between the isolation structure and the second gate structure, wherein the first interfacial layer and the second interfacial layer are an oxide of the semiconductor material.
Fig. 12B of Frougier teaches thin interfacial layers (Paragraph 0075 where a thin interfacial layer is grown during a preclean step of the channel regions) embedded in top and bottom surface of channel regions.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have a first interfacial layer embedded in the first ESL between the isolation structure and the first gate structure; and a second interfacial layer embedded in the second ESL between the isolation structure and the second gate structure, wherein the first interfacial layer and the second interfacial layer are an oxide of the semiconductor material because the interfacial layers are formed during a preclean step such that high-k dielectric material can be better grown on the semiconductor layers (Frougier Paragraph 0075).
Examiner’s Note: The Examiner notes that even though the layers in Chen indicated by the Examiner as first and second ESL layers are not explicitly labeled as ESL layers, the layers are capable of acting as ESL layers. This is all that is required by the claim as the claim is directed to a device and not a method such that no active etching is taking place.
Regarding claim 20, the combination of Chen and Frougier teaches all of the elements of the claimed invention as stated above.
Chen does not teach where, in a cross-section along a direction perpendicular to a longitudinal direction of the first channel regions, a first one of the first interfacial layer and the second interfacial layer has a rectangular shape.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have, in a cross-section along a direction perpendicular to a longitudinal direction of the first channel regions, a first one of the first interfacial layer and the second interfacial layer has a rectangular shape because the interfacial layers are formed during a preclean step such that high-k dielectric material can be better grown on the semiconductor layers (Frougier Paragraph 0075).
Regarding claim 24, under the alternate interpretation of Chen, Chen teaches all of the elements of the claimed invention as stated above.
Chen further teaches where the first ESL (Upper Item 106c) is a semiconductor material (Paragraph 0028).
Chen does not teach a first interfacial layer embedded in the first ESL between the isolation structure and the first gate structure; and a second interfacial layer embedded in the second ESL between the isolation structure and the second gate structure, wherein the first interfacial layer and the second interfacial layer comprise an oxide of the semiconductor material.
Fig. 12B of Frougier teaches thin interfacial layers (Paragraph 0075 where a thin interfacial layer is grown during a preclean step of the channel regions) embedded in top and bottom surface of channel regions.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have a first interfacial layer embedded in the first ESL between the isolation structure and the first gate structure; and a second interfacial layer embedded in the second ESL between the isolation structure and the second gate structure, wherein the first interfacial layer and the second interfacial layer comprise an oxide of the semiconductor material because the interfacial layers are formed during a preclean step such that high-k dielectric material can be better grown on the semiconductor layers (Frougier Paragraph 0075).
Regarding claim 25, the combination of Chen and Frougier teaches all of the elements of the claimed invention as stated above.
Chen further teaches where the first ESL (Lower 106c) comprises a center portion contacting the isolation structure (Combination of Items 2602, 2404 and 2403) and comprises end portions on opposing ends of the center portion.
Chen does not teach wherein the center portion of the first ESL is thinner than the end portions of the first ESL, wherein the first interfacial layer is between the first gate structure and the center portion of the first ESL.
Frougier further teaches where, during a preclean step, the channel layers are indented in the middle portion such that a middle portion of the channel region is thinner than end portions of the channel region (Paragraph 0075).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the center portion of the first ESL is thinner than the end portions of the first ESL, wherein the first interfacial layer is between the first gate structure and the center portion of the first ESL because the shape of the semiconductor layers, having a thinner middle portion than end portions, is formed during a preclean step such that high-k dielectric material can be better grown on the semiconductor layers (Frougier Paragraph 0075).
Allowable Subject Matter
Claims 15, 18, 19 and 26 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 15, the prior art does not teach, suggest or motive one having ordinary skill in the art to have, in a cross-section along a longitudinal direction of the plurality of channel regions, the first interfacial layer has a same thickness as the first ESL, or the second interfacial layer has a same thickness as the second ESL.
Regarding claim 18, the prior art does not teach, suggest or motive one having ordinary skill in the art to have, in a cross-section along a direction perpendicular to a longitudinal direction of the forts channel regions, a first one of the first interfacial layer and the second interfacial layer has a U-shape.
Claim 19 is also objected to as claim 19 includes all of the limitations of claim 18.
Regarding claim 26, the prior art does not teach, suggest or motive one having ordinary skill in the art to have the second interfacial layer and the second ESL have a same thickness.
Claim 27 is also objected to as claim 27 includes all of the limitations of claim 18.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC K ASHBAHIAN whose telephone number is (571)270-5187. The examiner can normally be reached 8-5:30 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at 571-272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERIC K ASHBAHIAN/Primary Examiner, Art Unit 2891