DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-16 have been considered but are moot because of the new ground of rejection due to new reference found, Morimoto et al. US 6,809,582 B2
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/20/2026. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3 & 9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Morimoto et al. (US 6,809,582 B2, hereinafter, Morimoto).
PNG
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684
1108
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454
1006
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Greyscale
Regarding claim 1:
Morimoto discloses in Figs. 1-2, 5, a semiconductor integrated circuit (Col. 3, lines 5-6, semiconductor device, and noise source NGb), comprising:
an input terminal (NGb, noise source), configured to allow inputting a signal of abrupt voltage change ;
an amplifier circuit (form by transistor 6 & 7 or CK), configured to amplify a difference between two input signals (IN+ and IN-);
a first element (diode 1, Fig. 1), connected to a first input end (IL1) of the amplifier circuit; and
a second element (diode 2, Fig. 1), connected to a second input end (IL2) of the amplifier circuit, wherein in a plan view, a distance between a first position (wherein the impurity region D1A) included in an arrangement region of the first element and a third position (noise source NGb) included in the input terminal is equal to a distance between a second position (the impurity region D2B) included in an arrangement region of the second element and the third position (see Col. 5, lines 5-20, when noise source NGb exists on the left side of impurity regions D1A and D2B in the figure, noise from noise source NGb arrives left sides PHc and PHd of impurity regions D1A and D2B, respectively. These impurity regions D1A and D2B are of the same area, arranged symmetrically about the position 5 of the center of gravity, and have the sides PHc and PHd away from noise source NGb by substantially the same distance. Therefore, noise of substantially the same amount reach the left sides PHc and PHd of impurity regions D1A and D2B).
Regarding claim 2:
Morimoto discloses wherein the first position (the impurity region D1A) is a central position of the arrangement region of the first element, the second position (D2B) is a central position of the arrangement region of the second element, and the third position (NGb, Fig. 5) is the central position of the input terminal.
Regarding claim 3:
Morimoto discloses wherein in the plan view, the first position and the second position are arranged symmetrically with respect to a central axis (center position 5, Fig. 5) passing through the third position of the input terminal.
Regarding claim 9:
Morimoto discloses wherein the input terminal is a digital signal terminal (NGb) configured to allow inputting a digital signal (Col. 2, lines 45-48, As the generation source of such noise, various circuits/ interconnection lines can be considered, including a digital circuit).
Allowable Subject Matter
Claims 4-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 4-8 are allowable since the closest prior art (i.e. Morimoto) does not discloses wherein the first element is a first capacitor, the second element is a second capacitor, the first capacitor includes: a first lower electrode, disposed above a semiconductor substrate; and a first upper electrode, disposed above the first lower electrode, the second capacitor includes: a second lower electrode, disposed above the semiconductor substrate; and a second upper electrode, disposed above the second lower electrode, the arrangement region of the first element is a region of the first upper electrode, and the arrangement region of the second element is a region of the second upper electrode.
Claims 10-16 are allowed.
The following is an examiner’s statement of reasons for allowance:
The amendment of independent claim 10 overcomes the previous rejections of the prior art including the reference of Morimoto et al. (US 6,809,582 B2, hereinafter, Morimoto). Specially, the independent claim 10 requires “first capacitor, including a first lower electrode disposed above the semiconductor substrate and a first upper electrode disposed above the first lower electrode; and a second capacitor comprising a second lower electrode above the semiconductor substrate and a second upper electrode above the second lower electrode, wherein the first upper electrode has a lower impedance than the first lower electrode”. As such, the combination of limitations of the independent claim 10 overcomes the prior art.
Claims 11-16 are allowable as being dependent on claim 10.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHIEM D NGUYEN whose telephone number is (571)270-3941. The examiner can normally be reached Mon-Fri 8:00 AM-5:00 PM EST.
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/KHIEM D NGUYEN/Examiner, Art Unit 2843
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