DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in JAPAN on 10/07/2022. It is noted, however, that applicant has not filed a certified copy of the JP2022162317 application as required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 09/27/2023. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 10-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Gregorian et al. (US 4,393,351), hereinafter, Gregorian).
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Regarding claim 10:
Gregorian discloses in Fig. 3 a semiconductor integrated circuit (Abstract which states “an integrator circuit”, comprising:
a semiconductor substrate (Col. 2, lines 27-28, which states a conductive substrate); and
a capacitor (capacitor 23 connected between node 17 and node 21, and Col. 2, lines 21-23, Capacitors are formed by utilizing layers of conductive material, such as metal or polycrystalline silicon), including a lower electrode (e.g., E1) disposed above the semiconductor substrate and an upper electrode (e.g., E2) disposed above the lower electrode (see example reference to Kobayashi, US 20130258148 A1, Fig. 1, low electrode 64 and layer 66 containing polysilicon functions as an upper electrode of the capacitor C and is connected to a terminal 68),
wherein the upper electrode (E2) has a lower impedance than the lower electrode.
Regarding claim 11:
Gregorian discloses the semiconductor integrated circuit of Claim 10, wherein the upper electrode is connected to a low impedance node (annotated node LZ1).
Regarding claim 12:
Gregorian discloses the semiconductor integrated circuit of Claim 11, wherein the low impedance node is an end to which a ground potential (ground) is applied.
Regarding claim 13:
Gregorian discloses the semiconductor integrated circuit of Claim 10, further comprising a low-pass filter (resistor 12 and capacitor 23 may for a low pass filter) including the capacitor and a resistor (see abstract, Gregorian discloses capacitor 16 and resistor are used interchangeably, thus capacitor 16 can be a resistor 12 as shown in Fig. 1).
Regarding claim 14:
Gregorian discloses the semiconductor integrated circuit of Claim 10, further comprising an operational amplifier (amplifier 19) including an input end (positive terminal) to which the lower electrode (LZ1, and where positive terminal and LZ1 both connected to ground) is connected.
Regarding claim 15:
Gregorian discloses the semiconductor integrated circuit of Claim 10, further comprising an input terminal (negative terminal or node 17) capacitively (capacitive of C23) coupled to the upper electrode (E1) and configured to allow inputting a signal of abrupt voltage change.
Regarding claim 16:
Gregorian discloses the semiconductor integrated circuit of Claim 15, wherein the input terminal (node 17 which capable of receiving a digital signal since circuit of Gregorian may be used in low amplification signal, see Fig. 4, digital signal) is a digital signal terminal configured to allow inputting a digital signal.
Allowable Subject Matter
Claims 1-9 are allowed.
Upon conclusion of a comprehensive search of the pertinent prior art, the Office indicates that the claims are allowable.
The prior art when taken alone, or, in combination, cannot be construed as reasonably teaching or suggesting all of the elements of the claimed invention as arranged, disposed, or provided in the manner as claimed by the Applicant. Added primarily for emphasis, the claim recitations “wherein in a plan view, a distance between a first position included in an arrangement region of the first element and a third position included in the input terminal is equal to a distance between a second position included in an arrangement region of the second element and the third position” in Claim 1 is not found in the prior art of record.
Claims 2-8 are allowable as being dependent of claim 1.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHIEM D NGUYEN whose telephone number is (571)270-3941. The examiner can normally be reached Mon-Fri 8:00 AM-5:00 PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, ANDREA J LINDGREN BALTZELL can be reached at (571)272-5918. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KHIEM D NGUYEN/Examiner, Art Unit 2843
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