DETAILED ACTION
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 6, 8, and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Burke (U.S. PGPub 20130323921).
Regarding claim 1, Burke teaches a method for manufacturing a trench field-effect transistor (FET), comprising: forming an epitaxial layer on a substrate, forming a trench in the epitaxial layer (Fig. 1, 12, 14, 58, [0013]-[0014]), forming a first insulating layer and a shielding conductor in the trench, wherein the first insulating layer surrounds the shielding conductor (Fig. 4, 126/127, 21, [0019]-[0020]), forming a dielectric layer on the epitaxial layer, the first insulating layer, and a side wall of the trench (Fig. 5, 132, [0021]), etching a part of the dielectric layer to form a dielectric region, wherein the dielectric region is located on the first insulating layer and the side wall of the trench (Fig. 6, [0022]), and forming a second insulating layer and a gate conductor in the trench, wherein the second insulating layer surrounds the gate conductor and fills the trench (Fig. 9, 134, 28, [0024], [0031]).
Regarding claim 2, Burke teaches wherein the etching a part of the dielectric layer to form a dielectric region further comprises: forming a plurality of dielectric regions on the side wall of the trench, wherein a spacing is formed between two adjacent dielectric regions (Fig. 6, [0022]).
Regarding claim 6, Burke teaches a method for manufacturing a trench field-effect transistor (FET) (Fig. 9), comprising: a substrate, an epitaxial layer, arranged on the substrate, a trench, arranged in the epitaxial layer, wherein the trench extends from a surface of the epitaxial layer into the epitaxial layer (Fig. 1, 12, 14, 58, [0013]-[0014]), an insulating layer, arranged in the trench (126/127/134, [0019]-[0020], [0024]), a shielding conductor, arranged in the trench, wherein the shielding conductor is surrounded by the insulating layer and insulated from the epitaxial layer through the insulating layer (21, [0019]-[0020]), a gate conductor, arranged in the trench, wherein the gate conductor is located on the shielding conductor and surrounded by the insulating layer and is insulated from the shielding conductor and the epitaxial layer through the insulating layer (28, [0031]), and a dielectric region, arranged between the shielding conductor and the gate conductor and located on a side wall of the trench (132, [0021]-[0022]).
Regarding claim 8, Burke teaches wherein a thickness of the insulating layer between the side wall of the trench and a side wall of the gate conductor ([0024], 134, 0.01-0.02 um) is less than a thickness of the insulating layer between the side wall of the trench and a side wall of the shielding conductor ([0018], 126, 0.04-0.06 um).
Regarding claim 10, Burke teaches wherein a plurality of dielectric regions are arranged, and when an even number of dielectric regions are arranged, the dielectric regions are symmetrical with respect to a center line of the gate conductor as an axis of symmetry (Fig. 9).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 3 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Burke (U.S. PGPub 20130323921).
Regarding claim 3, Burke teaches wherein the dielectric region is located between the shielding conductor and the gate conductor (Fig. 9), a distance between dielectric region and gate conductor is 0.01-0.02 um, [0024], and the dielectric region is separated from the shielding conductor by portions of layer 127, having thickness 0.1-0.3 um ([0020]) or the first insulating layer 126, having thickness 0.04-0.06 um ([0018]). In the case where the claimed ranges overlap or lie inside ranges disclosed by the prior art a prima facie case of obviousness exists. See MPEP 2144.05. Therefore it would have been obvious to a person having ordinary skill in the art to modify the teachings of Burke such that a distance between the dielectric region and the gate conductor is less than a distance between the dielectric region and the shielding conductor.
Regarding claim 7, Burke teaches wherein a distance between dielectric region and gate conductor is 0.01-0.02 um, [0024], and the dielectric region is separated from the shielding conductor by portions of layer 127, having thickness 0.1-0.3 um ([0020]) or layer 126, having thickness 0.04-0.06 um ([0018]). In the case where the claimed ranges overlap or lie inside ranges disclosed by the prior art a prima facie case of obviousness exists. See MPEP 2144.05. Therefore it would have been obvious to a person having ordinary skill in the art to modify the teachings of Burke such that a distance between the dielectric region and the gate conductor is less than a distance between the dielectric region and the shielding conductor.
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Burke (U.S. PGPub 20130323921).
Regarding claim 4, Burke teaches wherein the etching a part of the dielectric layer to form a dielectric region comprises etching a part of the dielectric layer to form two dielectric regions on the first insulating layer and the two opposite sidewalls of the trench ([0022], Fig. 6), but does not explicitly teach wherein the etching comprises:
etching a part of the dielectric layer located on the epitaxial layer, the first insulating layer, and the side wall of the trench through reactive ions, to form the dielectric layers respectively located on two opposite side walls of the trench, wherein the dielectric layers on the two opposite side walls of the trench are not connected to each other, and adjusting gas flow and a reaction time of a reactive ion gas, and etching a part of the dielectric layers located on the two opposite side walls of the trench again through the reactive ions.
Tsai teaches wherein selectively recessing a dielectric layer formed in a trench in an epitaxial layer is performed by etching in separate etching steps using RIE, and tuning etching parameters including etchant flow rate and time ([0038]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Tsai with Burke such that the etching comprises etching a part of the dielectric layer located on the epitaxial layer, the first insulating layer, and the side wall of the trench through reactive ions, to form the dielectric layers respectively located on two opposite side walls of the trench, wherein the dielectric layers on the two opposite side walls of the trench are not connected to each other, and adjusting gas flow and a reaction time of a reactive ion gas, and etching a part of the dielectric layers located on the two opposite side walls of the trench again through the reactive ions for the purpose of using a known suitable etching technique, controlled for selective etching, to achieve the dielectric regions of Burke.
Regarding claim 5, Burke teaches wherein the etching a part of the dielectric layer to form a dielectric region comprises wet etching a part of the dielectric layer to form two dielectric regions on the first insulating layer and the two opposite sidewalls of the trench ([0022], Fig. 6), but does not explicitly teach wherein the etching comprises:
etching the dielectric layer on the epitaxial layer and a part of the dielectric layer in the trench through wet etching, and adjusting an etching solution concentration and an etching time for the wet etching, and etching the part of the dielectric layer located in the trench again through the wet etching.
Tsai teaches wherein selectively recessing a dielectric layer formed in a trench in an epitaxial layer is performed by etching in separate etching steps using wet etching, and tuning etching parameters including etching solution concentration and etching time ([0038]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Tsai with Burke such that the etching comprises etching the dielectric layer on the epitaxial layer and a part of the dielectric layer in the trench through wet etching, and adjusting an etching solution concentration and an etching time for the wet etching, and etching the part of the dielectric layer located in the trench again through the wet etching for the purpose of using a known suitable etching technique, controlled for selective etching, to achieve the dielectric regions of Burke.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Burke (U.S. PGPub 20130323921) in view of Pan (U.S. PGPub 20100006928).
Regarding claim 9, Burke teaches wherein a plurality of dielectric regions are arranged (Fig. 6) but does not explicitly teach wherein each of the dielectric regions is made of a low dielectric constant material, and a dielectric constant of the low dielectric constant material is less than 3.9.
Pan teaches wherein a dielectric region formed between a shielding conductor and a gate conductor is formed of a low dielectric constant material (Fig. 3I, 328, 314, [0042], [0031]; 318, [0031]-[0032], low-k dielectric is defined as less than 3.9).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Pan with Burke such that each of the dielectric regions is made of a low dielectric constant material, and a dielectric constant of the low dielectric constant material is less than 3.9 for the purpose of reducing thickness sensitivity of the inter-electrode dielectric (Pan, [0023]).
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
20120235229
20190006479
Wang et al. (2020). Shield Gate Trench MOSFET with Narrow Gate Architecture and Low-k Dielectric Layer. IEEE Electron Device Letters. PP. 1-1. 10.1109/LED.2020.2981484.
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/ALIA SABUR/ Primary Examiner, Art Unit 2812