DETAILED ACTION
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-3 and 6-10 are rejected under 35 U.S.C. 103 as being unpatentable over Li (CN 111681963 A) in view of Pan (U.S. PGPub 20100006928).
Regarding claim 1, Li teaches a method for manufacturing a trench field-effect transistor (FET), comprising: forming a trench in a substrate (Fig. 2, 100, 110, [0053]), forming a first insulating layer and a shielding conductor in the trench, wherein the first insulating layer surrounds the shielding conductor (Fig. 3, 200, 300, [0057]), forming a dielectric layer that is in direct contact with the substrate, the first insulating layer, and a side wall of the trench (Fig. 5, 400, [0063]), etching a part of the dielectric layer to form a dielectric region, wherein the dielectric region is located on the first insulating layer and the side wall of the trench (Fig. 7, [0077]), and forming a second insulating layer and a gate conductor in the trench, wherein the second insulating layer surrounds the gate conductor and fills the trench (Fig. 8, 500/600, 700, [0081]-[0084]).
Li does not explicitly teach forming an epitaxial layer on a substrate and forming the trench in the epitaxial layer.
Pan teaches wherein a trench field-effect transistor is formed in a trench formed in an epitaxial layer over the substrate ([0045]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Pan with Li such that the method comprises forming an epitaxial layer on a substrate and forming the trench in the epitaxial layer because the prior art teaches every element, a person of ordinary skill could have combined them as claimed and in combination each element performs the same function as it does separately, and the combination would have yielded predictable results to one of ordinary skill in the art before the time of the invention. See MPEP 2143(I)A.
Regarding claim 2, Li teaches wherein the etching a part of the dielectric layer to form a dielectric region further comprises: forming a plurality of dielectric regions on the side wall of the trench, wherein a spacing is formed between two adjacent dielectric regions (Fig. 7).
Regarding claim 3, Li teaches wherein the dielectric region is located between the shielding conductor and the gate conductor, and a distance between the dielectric region and the gate conductor is less than a distance between the dielectric region and the shielding conductor (Fig. 8, drawing relied upon for relative spacing and not absolute spacing).
Regarding claim 6, Li teaches a method for manufacturing a trench field-effect transistor (FET) (Fig. 8), comprising: a substrate, a trench in the substrate, wherein the trench extends from a surface of the epitaxial layer into the epitaxial layer (Fig. 2, 100, 110, [0053]), an insulating layer, arranged in the trench (Fig. 3, 200, [0057]), a shielding conductor, arranged in the trench, wherein the shielding conductor is surrounded by the insulating layer and insulated from the substrate through the insulating layer (Fig. 3, 300, [0057]), a gate conductor, arranged in the trench, wherein the gate conductor is located on the shielding conductor and surrounded by the insulating layer and is insulated from the shielding conductor and the epitaxial layer through the insulating layer (Fig. 8, 700, [0081]), and a dielectric region, arranged between the shielding conductor and the gate conductor and located on a side wall of the trench and in direct contact with the sidewall of the trench and the insulating layer (Fig. 8, 400, [0077], [0092]).
Li does not explicitly teach an epitaxial layer on the substrate, wherein the trench is in the epitaxial layer.
Pan teaches wherein a trench field-effect transistor is formed in a trench formed in an epitaxial layer over the substrate ([0045]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Pan with Li such that the device comprises an epitaxial layer on the substrate, wherein the trench is in the epitaxial layer because the prior art teaches every element, a person of ordinary skill could have combined them as claimed and in combination each element performs the same function as it does separately, and the combination would have yielded predictable results to one of ordinary skill in the art before the time of the invention. See MPEP 2143(I)A.
Regarding claim 7, Li teaches wherein a distance between the dielectric region and the gate conductor is less than a distance between the dielectric region and the shielding conductor (Fig. 8, drawing relied upon for relative spacing and not absolute spacing).
Regarding claim 8, Li teaches wherein a thickness of the insulating layer between the side wall of the trench and a side wall of the gate conductor is less than a thickness of the insulating layer between the side wall of the trench and a side wall of the shielding conductor (Fig. 8, [0071], [0083]).
Regarding claim 9, Li teaches wherein a plurality of dielectric regions are arranged (Fig. 8) but does not explicitly teach wherein each of the dielectric regions is made of a low dielectric constant material, and a dielectric constant of the low dielectric constant material is less than 3.9.
Pan teaches wherein a dielectric region formed between a shielding conductor and a gate conductor is formed of a low dielectric constant material (Fig. 3I, 328, 314, [0042], [0031]; 318, [0031]-[0032], low-k dielectric is defined as less than 3.9).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Pan with Li such that each of the dielectric regions is made of a low dielectric constant material, and a dielectric constant of the low dielectric constant material is less than 3.9 for the purpose of reducing thickness sensitivity of the inter-electrode dielectric (Pan, [0023]).
Regarding claim 10, Li teaches wherein a plurality of dielectric regions are arranged, and when an even number of dielectric regions are arranged, the dielectric regions are symmetrical with respect to a center line of the gate conductor as an axis of symmetry (Fig. 8).
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Li (CN 111681963 A) in view of Pan (U.S. PGPub 20100006928) and Tsai (U.S. PGPub 2019/0067020).
Regarding claim 4, Li teaches wherein the etching a part of the dielectric layer to form a dielectric region comprises etching a part of the dielectric layer to form two dielectric regions on the first insulating layer and the two opposite sidewalls of the trench (Fig. 7), but does not explicitly teach wherein the etching comprises:
etching a part of the dielectric layer located on the epitaxial layer, the first insulating layer, and the side wall of the trench through reactive ions, to form the dielectric layers respectively located on two opposite side walls of the trench, wherein the dielectric layers on the two opposite side walls of the trench are not connected to each other, and adjusting gas flow and a reaction time of a reactive ion gas, and etching a part of the dielectric layers located on the two opposite side walls of the trench again through the reactive ions.
Tsai teaches wherein selectively recessing a dielectric layer formed in a trench in an epitaxial layer is performed by etching in separate etching steps using RIE, and tuning etching parameters including etchant flow rate and time ([0038]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Tsai with Li such that the etching comprises etching a part of the dielectric layer located on the epitaxial layer, the first insulating layer, and the side wall of the trench through reactive ions, to form the dielectric layers respectively located on two opposite side walls of the trench, wherein the dielectric layers on the two opposite side walls of the trench are not connected to each other, and adjusting gas flow and a reaction time of a reactive ion gas, and etching a part of the dielectric layers located on the two opposite side walls of the trench again through the reactive ions for the purpose of using a known suitable etching technique, controlled for selective etching, to achieve the dielectric regions of Li.
Regarding claim 5, Li teaches wherein the etching a part of the dielectric layer to form a dielectric region comprises etching a part of the dielectric layer to form two dielectric regions on the first insulating layer and the two opposite sidewalls of the trench (Fig. 7), but does not explicitly teach wherein the etching comprises:
etching the dielectric layer on the epitaxial layer and a part of the dielectric layer in the trench through wet etching, and adjusting an etching solution concentration and an etching time for the wet etching, and etching the part of the dielectric layer located in the trench again through the wet etching.
Tsai teaches wherein selectively recessing a dielectric layer formed in a trench in an epitaxial layer is performed by etching in separate etching steps using wet etching, and tuning etching parameters including etching solution concentration and etching time ([0038]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Tsai with Li such that the etching comprises etching the dielectric layer on the epitaxial layer and a part of the dielectric layer in the trench through wet etching, and adjusting an etching solution concentration and an etching time for the wet etching, and etching the part of the dielectric layer located in the trench again through the wet etching for the purpose of using a known suitable etching technique, controlled for selective etching, to achieve the dielectric regions of Li.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ALIA SABUR/ Primary Examiner, Art Unit 2812
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