DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1, 7, and 13 have been amended.
Claims 1-18 have been examined.
The § 112 rejections in the previous Office Action have been addressed and are withdrawn.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on March 12, 2026 has been entered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the Applicant regards as the invention.
Claim 1 recites, “the performed sub-operation.” There is insufficient antecedent basis for this limitation in the claim. Claims 7 and 13 include similar limitations and are similarly rejected.
Claims 2-6, 8-12, and 14-18 are rejected as depending from rejected base claims and failing to cure the indefiniteness of those base claims.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 6, 7, 9, 13, 15 are rejected under 35 U.S.C. 103 as being unpatentable over US Publication No. 2021/0240482 by Chevobbe et al. (hereinafter referred to as “Chevobbe”) in view of US Publication No. 2014/0365752 by Howes et al. (hereinafter referred to as “Howes”).
Regarding claim 1, Chevobbe discloses:
a processing array comprising: a plurality of processors (Chevobbe discloses, at Figure 1 and related description, an array of processing elements (PEs).); and
a plurality of finite state machines, wherein each respective finite state machine among the plurality of finite state machines is communicatively coupled to a respective processor among the plurality of processors (Chevobbe discloses, at Figure 2 and related description, each PE includes a finite state machine (FSM) used in processing data.),
wherein each processor of the plurality of processors is configured to execute… a same global instruction concurrently and each processor is configured to selectively utilize a corresponding finite state machine to perform a set of sub-operations… wherein executing the same global instruction is performed… (Chevobbe discloses, at ¶ [0025], a SIMD processor in which each of the processors executes the same instruction in parallel, which discloses executing a same global instruction concurrently. As disclosed at Figure 2 and related description, the execution utilizes the FSMs.).
Chevobbe does not explicitly disclose the aforementioned processors each execute a different thread, a data-dependent control loop that is performed to execute the aforementioned same global instruction, and wherein the performed sub-operation is different for at least some of the plurality of finite state machines
However, in the same field of endeavor (e.g., processing) Howes discloses:
executing different threads (Howes discloses, at ¶ [0028], executing different work items at different processors. As disclosed at ¶ [0022], work items are threads executed in parallel.);
performing a data-dependent control loop (Howes discloses, at ¶ [0028], a while loop that executes until a specific condition is met, which discloses performing a data-dependent control loop.); and
executing different sub-operations (Howes discloses, at ¶ [0028], work items diverge, which discloses executing different sub-operations.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Chevobbe to include thread execution, data-dependent control loops, and divergent sub-operations, as disclosed by Howes, in order to improve performance by providing efficient and flexible synchronization. See Howe, ¶ [0008].
Regarding claim 6, Chevobbe discloses the elements of claim 1, as discussed above. Chevobbe also discloses:
wherein each respective processor among the plurality of processors is further configured to merge results of processing the data with one or more other processors among the plurality of processors (Chevobbe discloses, at ¶ [0063] et seq., each PE notifies the central controller of completion and the process is repeated until the program is complete, e.g., all data in an image is processed, which discloses merging the results.).
Regarding claim 7, Chevobbe discloses:
a method for processing data, the method comprising: receiving, by a processing array, a request to process the data, wherein the processing array includes a plurality of processors (Chevobbe discloses, at Figure 1 and related description, an array of processing elements (PEs) receiving an instruction from a central controller, which discloses a request to process data.);
in response to the request, configuring the plurality of processors to utilize a plurality of finite state machines (Chevobbe discloses, at ¶ [0035], the PE determines whether the received identifier relates to the PE and if so, uses the FSM to process data.); and
processing the data using the plurality of finite state machine and the plurality of processors, each processor of the plurality of processors executing … a same global instruction concurrently and each processor is configured to selectively utilize a corresponding finite state machine selected by the global instruction to perform a set of sub-operations … wherein executing the same global instruction is performed … (Chevobbe discloses, at ¶ [0025], a SIMD processor in which each of the processors executes the same instruction in parallel, which discloses executing a same global instruction concurrently. As disclosed at Figure 2 and related description, the execution utilizes the FSMs.).
Chevobbe does not explicitly disclose the aforementioned processors each execute a different thread, a data-dependent control loop that is performed to execute the aforementioned same global instruction, and wherein the performed sub-operation is different for at least some of the plurality of finite state machines
However, in the same field of endeavor (e.g., processing) Howes discloses:
executing different threads (Howes discloses, at ¶ [0028], executing different work items at different processors. As disclosed at ¶ [0022], work items are threads executed in parallel.);
performing a data-dependent control loop (Howes discloses, at ¶ [0028], a while loop that executes until a specific condition is met, which discloses performing a data-dependent control loop.); and
executing different sub-operations (Howes discloses, at ¶ [0028], work items diverge, which discloses executing different sub-operations.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Chevobbe to include thread execution, data-dependent control loops, and divergent sub-operations, as disclosed by Howes, in order to improve performance by providing efficient and flexible synchronization. See Howe, ¶ [0008].
Regarding claim 9, Chevobbe discloses the elements of claim 7, as discussed above. Chevobbe also discloses:
the request is included in the same global instruction (Chevobbe discloses, at Figure 1 and related description, an array of processing elements (PEs) receiving an instruction from a central controller, which discloses a request to process data, including the global instruction.).
Regarding claim 13, Chevobbe discloses:
…instructions for processing data, the instructions when executed by a processing array, cause the processing array to execute a method that includes: receiving, by the processing array, a request to process the data, wherein the processing array includes a plurality of processors (Chevobbe discloses, at Figure 1 and related description, an array of processing elements (PEs) receiving an instruction from a central controller, which discloses a request to process data.);
in response to the request, configuring the plurality of processors to utilize a plurality of finite state machines (Chevobbe discloses, at ¶ [0035], the PE determines whether the received identifier relates to the PE and if so, uses the FSM to process data.); and
processing the data using the plurality of finite state machines and the plurality of processors wherein each processor of the plurality of processors is configured to execute … a same global instruction concurrently and each processor is configured to selectively utilize a corresponding finite state machine to perform a set of sub-operations … wherein executing the same global instruction is performed … (Chevobbe discloses, at ¶ [0025], a SIMD processor in which each of the processors executes the same instruction in parallel, which discloses executing a same global instruction concurrently. As disclosed at Figure 2 and related description, the execution utilizes the FSMs.).
Chevobbe does not explicitly disclose a non-transitory computer readable storage medium, storing the aforementioned instructions, the aforementioned processors each execute a different thread, a data-dependent control loop that is performed to execute the aforementioned same global instruction, and wherein the performed sub-operation is different for at least some of the plurality of finite state machines
However, in the same field of endeavor (e.g., processing) Howes discloses:
a non-transitory computer readable storage medium (Howes discloses, at claim 19,a non-transitory computer readable storage medium.);
executing different threads (Howes discloses, at ¶ [0028], executing different work items at different processors. As disclosed at ¶ [0022], work items are threads executed in parallel.);
performing a data-dependent control loop (Howes discloses, at ¶ [0028], a while loop that executes until a specific condition is met, which discloses performing a data-dependent control loop.); and
executing different sub-operations (Howes discloses, at ¶ [0028], work items diverge, which discloses executing different sub-operations.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Chevobbe to include a non-transitory computer readable storage medium, thread execution, data-dependent control loops, and divergent sub-operations, as disclosed by Howes, in order to improve performance by providing efficient and flexible synchronization. See Howe, ¶ [0008].
Regarding claim 15, Chevobbe discloses the elements of claim 13, as discussed above. Chevobbe also discloses:
the request is included in the same global instruction (Chevobbe discloses, at Figure 1 and related description, an array of processing elements (PEs) receiving an instruction from a central controller, which discloses a request to process data, including the global instruction.).
Claims 2, 8, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Chevobbe in view of Howes in view of US Publication No. 2023/0315479 by Thuerck (hereinafter referred to as “Thuerck”).
Regarding claim 2, Chevobbe discloses the elements of claim 1, as discussed above. Chevobbe does not explicitly disclose wherein the plurality of finite state machines implement sparse linear algebra operations.
However, in the same field of endeavor (e.g., processing) Thuerck discloses:
implementing sparse linear algebra operations (Thuerck discloses, at ¶ [0062], sparse matrix operations.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Chevobbe to include sparse linear algebra operations, as taught by Thueck, because these operations are commonly utilized in modern computing and supporting such operations increases the utility of a processor. See, e.g., Thueck, ¶ [0007].
Regarding claim 8, Chevobbe discloses the elements of claim 7, as discussed above. Chevobbe does not explicitly disclose wherein the respective finite state machine implements sparse linear algebra operations.
However, in the same field of endeavor (e.g., processing) Thuerck discloses:
implementing sparse linear algebra operations (Thuerck discloses, at ¶ [0062], sparse matrix operations.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Chevobbe to include sparse linear algebra operations, as taught by Thueck, because these operations are commonly utilized in modern computing and supporting such operations increases the utility of a processor. See, e.g., Thueck, ¶ [0007].
Regarding claim 14, Chevobbe discloses the elements of claim 13, as discussed above. Chevobbe does not explicitly disclose wherein the respective finite state machine implements sparse linear algebra operations.
However, in the same field of endeavor (e.g., processing) Thuerck discloses:
implementing sparse linear algebra operations (Thuerck discloses, at ¶ [0062], sparse matrix operations.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Chevobbe to include sparse linear algebra operations, as taught by Thueck, because these operations are commonly utilized in modern computing and supporting such operations increases the utility of a processor. See, e.g., Thueck, ¶ [0007].
Claims 3-5, 10-12, and 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Chevobbe in view of Howes in view of US Publication No. 2022/010025 by Bharadwaj et al. (hereinafter referred to as “Bhradwaj”).
Regarding claim 3, Chevobbe, as modified, discloses the elements of claim 1, as discussed above. Chevobbe also discloses:
wherein each respective processor among the plurality of processors is configured to selectively utilize a corresponding finite state machine in processing data based on a hint …(Chevobbe discloses, at ¶ [0029], a central controller that transmits an instruction to the processing elements. As disclosed at ¶ [0032], the instruction includes an identifier, i.e., hint. Chevobbe discloses, at ¶ [0035], the PE determines whether the received identifier relates to the PE and if so, uses the FSM to process data.).
Chevobbe does not explicitly disclose the aforementioned hint is included in the global instruction.
However, in the same field of endeavor (e.g., processing) Bharadwaj discloses:
instructions providing hints (Bharadwaj discloses, at ¶ [0014], instructions that include hints.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Chevobbe to include hints in the instructions, as disclosed by Bharadwaj, in order to improve performance by providing an efficient control mechanism.
Regarding claim 4, Chevobbe discloses the elements of claim 3, as discussed above. Chevobbe also discloses:
the hint causes a subset of the plurality of processors to utilize the respective finite state machine in processing of the data (Chevobbe discloses, at ¶ [0035], the PE determines whether the received identifier relates to the PE and if so, uses the FSM to process data and if not, does not, which discloses causing a subset of the PEs to utilize the FSM.).
Regarding claim 5, Chevobbe discloses the elements of claim 4, as discussed above. Chevobbe also discloses:
the subset processes the data asynchronously with respect to a remainder of the plurality of processors not included in the subset (Chevobbe discloses, at ¶ [0048], asynchronously processing the data.).
Regarding claim 10, Chevobbe discloses the elements of claim 7, as discussed above. Chevobbe also discloses:
…the request causes a subset of the plurality of processors to utilize the respective finite state machine in the processing of the data (Chevobbe discloses, at ¶ [0035], the PE determines whether the received identifier relates to the PE and if so, uses the FSM to process data and if not, does not, which discloses causing a subset of the PEs to utilize the FSM.).
Chevobbe does not explicitly disclose a hint of the request.
However, in the same field of endeavor (e.g., processing) Bharadwaj discloses:
instructions providing hints (Bharadwaj discloses, at ¶ [0014], instructions that include hints, which discloses the request including the hint.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Chevobbe to include hints in the instructions, as disclosed by Bharadwaj, in order to improve performance by providing an efficient control mechanism.
Regarding claim 11, Chevobbe discloses the elements of claim 10, as discussed above. Chevobbe also discloses:
the subset processes the data asynchronously with respect to a remainder of the plurality of processors not included in the subset (Chevobbe discloses, at ¶ [0048], asynchronously processing the data.).
Regarding claim 12, Chevobbe discloses the elements of claim 11, as discussed above. Chevobbe also discloses:
merging results of processing the data with one or more other processors among the plurality of processors (Chevobbe discloses, at ¶ [0063] et seq., each PE notifies the central controller of completion and the process is repeated until the program is complete, e.g., all data in an image is processed, which discloses merging the results.).
Regarding claim 16, Chevobbe discloses the elements of claim 13, as discussed above. Chevobbe also discloses:
…the request causes a subset of the plurality of processors to utilize the respective finite state machine in the processing of the data (Chevobbe discloses, at ¶ [0035], the PE determines whether the received identifier relates to the PE and if so, uses the FSM to process data and if not, does not, which discloses causing a subset of the PEs to utilize the FSM.).
Chevobbe does not explicitly disclose a hint of the request.
However, in the same field of endeavor (e.g., processing) Bharadwaj discloses:
instructions providing hints (Bharadwaj discloses, at ¶ [0014], instructions that include hints, which discloses the request including the hint.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Chevobbe to include hints in the instructions, as disclosed by Bharadwaj, in order to improve performance by providing an efficient control mechanism.
Regarding claim 17, Chevobbe discloses the elements of claim 16, as discussed above. Chevobbe also discloses:
the subset processes the data asynchronously with respect to a remainder of the plurality of processors not included in the subset (Chevobbe discloses, at ¶ [0048], asynchronously processing the data.).
Regarding claim 18, Chevobbe discloses the elements of claim 17, as discussed above. Chevobbe also discloses:
merging results of processing the data with one or more other processors among the plurality of processors (Chevobbe discloses, at ¶ [0063] et seq., each PE notifies the central controller of completion and the process is repeated until the program is complete, e.g., all data in an image is processed, which discloses merging the results.).
Response to Arguments
On pages 9-10 of the response filed March 12, 2026 (“response”), the Applicant argues, “Page 3 of the Office Action indicates that Chevobbe does not disclose the recited data-dependent control loop defined by the same global instruction, and cites to Howes as teaching this feature. Applicants submit that Howes does not teach this feature as amended. In particular, page 3 of the Office Action cites to a while loop described at paragraph [0028] of Howes. Applicants submit, however, that this while loop is not the same as what is recited in claims 1, 7, and 13. In particular, claims 1, 7, and 13 recite that executing the same global instruction is performed by executing the data dependent control loop. Howes does not describe this. Instead, Howes just discloses a while loop, in general. For example, paragraph [0028] of Howes states "program part 102 illustrates an example divergent control flow through the use of a "while(a)" loop which is executed based upon a conditional value. The control flow may diverge between respective workitems of a SIMD vector thread executing the code, with some of the workitems entering the while(a) loop and waiting until a conditional value (e.g., variable "a") is updated by another workitem which may not enter the while(a) loop." There is no mention here of a same global instruction, or that "executing the same global instruction is performed by executing the data dependent control loop." Again, the while loop of Howes appears to just be a generic while loop that is not involved in or associated in any way with executing a "same global instruction" as recited in claims 1, 7, and 13. For at least this reason, Applicants submit that the cited references cannot teach or suggest each and every feature of claims 1, 7, and 13.”
Though fully considered, the Examiner respectfully disagrees. The Applicant is arguing references individually, which is not persuasive. See MPEP § 2145(IV). The Applicant argues that Howes does not mention a same global instruction. Howe is not cited as disclosing the same global instruction. Instead, Chevobbe discloses the same global instruction. Howe is cited as using a data dependent control loop, e.g., a while loop, to execute instructions. It would have been obvious to modify Chevobbe to use the data dependent control loop disclosed by Howe in the execution of Chevobbe’s same global instruction because while loops are simple and efficient mechanisms to allow dynamic control, not to mention being fundamentally well-known. Together, the combination discloses all elements of Applicant’s claims. Accordingly, the Applicant’s arguments are deemed unpersuasive.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAWN DOMAN whose telephone number is (571)270-5677. The examiner can normally be reached on Monday through Friday 8:30am-6pm Eastern Time.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHAWN DOMAN/Primary Examiner, Art Unit 2183
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