DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Group I in the reply filed on 1/26/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claims 11-14 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 1/26/2026.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 9/27/2023, 12/2/2024, 2/21/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 15 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kang et al (US 2011/0303931; hereinafter Kang).
Regarding claim 15, Figs 3, 5-6 of Kang discloses a micro LED structure (Fig 3) comprising an active layer structure (109; Fig 3; ¶ [0051]) comprising a multi-quantum well structure (¶ [0051]) of III-V nitride materials which is configured to emit light under application of an operating voltage or under optical excitation (¶ [0014]), wherein under application of an operating voltage or under optical excitation, the multi quantum well structure exhibits an emission wavelength uniformity of +/- 3 nm or less or of +/- 1 nm or less (¶ [0080]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 4-8, 10 are rejected under 35 U.S.C. 103 as being unpatentable over Araki et al (US 2013/0277684; hereinafter Araki) in view of Sundaram et al (US 2016/0203972; hereinafter Sundaram).
Regarding claim 1, Fig 1 of Araki discloses a GaN-on-Si epiwafer forming a layer stack (Fig 1) comprising along a stacking direction:
a substrate (1/2; Fig 1; ¶ [0155]) having a diameter of 150 mm or more, preferably, of 150 mm to 450 mm (¶ [0149]), in at least one direction that is perpendicular to the stacking direction (Fig 1) and a substrate surface along the stacking direction that is at least partly formed by silicon (¶ [0009]),
a strain-decoupling sub-stack (4/5/7/9/11/13/15; Fig 1) comprising
a self-organized template layer (4; Fig 1; ¶ [0155]) arranged directly on the substrate, the self-organized template layer comprising pits (4; Fig 1; ¶ [0186]), said pits having a pit density of 1x107 cm-2 to 1x1011 cm-2 (¶ [0186]), and
a surface recovery layer (5; Fig 1; ¶ [0155]) arranged directly on the self-organized template layer (4; Fig 1; ¶ [0155]) and comprising GaN (¶ [0219]), the surface recovery layer (5; Fig 1; ¶ [0155]) having a substantially smooth surface pointing (Fig 1) along the stacking direction, and
a strain-engineering sub-stack (7/9; Fig 1; ¶ [0155]) arranged on the surface recovery layer (5; Fig 1; ¶ [0155]) and comprising at least one GaN layer (7; Fig 1; ¶ [0226]) and at least one AlxGa1-xN intermediate layer (9; Fig 1; ¶ [0231]), with x > 0.5, the GaN layer having a thickness of 0.5 µm to 4.0 µm (4.0 µm; ¶ [0229]), the AlxGa1-xN intermediate layer having a thickness of 5 nm to 25 nm (¶ [0232]).
However Araki does not expressly disclose the GaN-on-Si epiwafer has a bow of at most 100 µm at room temperature.
In the same field of endeavor, Fig 3 of Sundaram discloses a GaN-on-Si epiwafer has a bow of at most 100 µm at room temperature (¶ [0089]).
Accordingly it would have been obvious to the person in the ordinary skill in the art before the effective filing date of the invention such that a GaN-on-Si epiwafer has a bow of at most 100 µm as this specification is required for using the wafers in the automated wafer handling systems that are integrated into high volume production (¶ [0089]).
Regarding claim 2, Fig 1 of Araki discloses an active layer structure (11; Fig 1; ¶ [0155]) arranged on the strain-engineering sub-stack (7/9; Fig 1; ¶ [0155]), the active layer structure (11; Fig 1; ¶ [0155]) comprising a multi- quantum-well structure of III-V nitride materials (¶ [0239]), which is configured to emit light under application of an operating voltage or under optical excitation, and/or comprising a lasing structure configured for emitting laser radiation and/or comprising a transistor structure (¶ [0239]).
Regarding claim 4, Fig 1 of Araki discloses the self-organized template layer (4; Fig 1; ¶ [0155]) has a total dislocation density of 109 cm-2 or more throughout a thickness of the self-organized template layer (¶ [0186]).
Regarding claim 5, Fig 1 of Araki discloses the self-organized template layer (4; Fig 1; ¶ [0155]) comprises line defects of which at least 50% or at least 70% or at least 90% (¶ [0186]) have an angle with respect to the stacking direction of 0° to 20° or in the range of 0° to 2° (Fig 1).
Regarding claim 6, Fig 1 of Araki discloses the strain engineering sub-stack comprises at least two repetitions of a sequence of the GaN layer and the AlxGa1-xN intermediate layer (9; Fig 1; ¶ [0231]).
Regarding claim 7, Fig 1 of Araki discloses the smooth surface of the surface recovery layer (5; Fig 1; ¶ [0155]).
However Araki does not expressly disclose the smooth surface of the surface recovery layer has a reflectivity of 35% or more.
However, the ordinary artisan would have recognized the materials of the surface recovery layer and the smoothness of the surface recovery layer to be a result effective variable affecting reflectivity. Thus, it would have been obvious to vary the materials and level of smoothness in order to achieve the reflectivity within the claimed range, since optimum or workable ranges of such variables are discoverable through routine experimentation. see MPEP 2144.05 II.B
Regarding claim 8, Fig 1 of Araki discloses the surface recovery layer comprises dislocations that bend under an angle of 15° to 45° with respect to an interface formed between the self-organized template layer and the surface recovery layer. (¶ [0218]; Figs 8-11)
Regarding claim 10, Fig 1 of Araki discloses the pits (4; Fig 1; ¶ [0186]) of the self-organized template layer have an average pit distance between adjacent pits that is in the range of 200 nm to 2000 nm (¶ [0289]).
Claim(s) 9 is rejected under 35 U.S.C. 103 as being unpatentable over Araki et al (US 2013/0277684; hereinafter Araki) in view of Sundaram et al (US 2016/0203972; hereinafter Sundaram) and further in view of Liu (US 2012/0126201; hereinafter Liu).
Regarding claim 9, Araki does not expressly disclose pits of the self-organized template layer have a pit size of 1 nm to 100 nm.
In the same field of endeavor, Liu discloses pits are formed in a semiconductor layer and pit size is 50 nm (¶ [0041]).
Accordingly it would have been obvious to the person in the ordinary skill in the art before the effective filing date of the invention such that pits are formed in the self-organized template layer and having pit size of 1 nm to 100 nm as the pit density is dependent on size of the pits and hence the resulting active layer can have higher quality due to less stress (¶ [0041]).
Claim(s) 3 is rejected under 35 U.S.C. 103 as being unpatentable over Araki et al (US 2013/0277684; hereinafter Araki) in view of Sundaram et al (US 2016/0203972; hereinafter Sundaram) and further in view of Kang (US 2011/0303931; hereinafter Kang).
Regarding claim 3, Fig 1 of Araki discloses under application of an operating voltage or under optical excitation, the multi-quantum well structure exhibits an emission wavelength (¶ [0261]).
However Araki does not expressly disclose a wavelength uniformity of +/- 3 nm or less or of +/- 1 nm or less.
In the same field of endeavor, Fig 6 of Kang discloses under an application of an operating voltage, the active layer exhibits an emission wavelength having a wavelength uniformity of +/- 3 nm or less (¶ [0080]).
Accordingly it would have been obvious to the person in the ordinary skill in the art before the effective filing date of the invention such as the wavelength uniformity can be within the claimed range in order to achieve the LED with improved yield (¶ [0071]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Pinos et al (US 2023/0238479)
Tan et al (US 2023/0130445)
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RATISHA MEHTA whose telephone number is (571)270-7473. The examiner can normally be reached Monday-Friday: 9:00am - 5:00 pm.
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/RATISHA MEHTA/ Primary Examiner, Art Unit 2817
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