Office Action Predictor
Last updated: April 15, 2026
Application No. 18/476,000

Component Carrier and Method of Manufacturing the Same

Final Rejection §102
Filed
Sep 27, 2023
Examiner
WILLIS, TREMESHA S
Art Unit
2847
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
At&S (Chongqing) Company Limited
OA Round
2 (Final)
78%
Grant Probability
Favorable
3-4
OA Rounds
2y 6m
To Grant
99%
With Interview

Examiner Intelligence

Grants 78% — above average
78%
Career Allow Rate
679 granted / 873 resolved
+9.8% vs TC avg
Strong +22% interview lift
Without
With
+22.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
44 currently pending
Career history
917
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
31.6%
-8.4% vs TC avg
§102
49.6%
+9.6% vs TC avg
§112
16.9%
-23.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 873 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Amendment Applicant's arguments with respect to claims 1 – 28 have been considered but are moot in view of the new ground(s) of rejection. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1 – 28 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yoshimura et al. (U.S. Patent Publication No. 2009/0294161). Regarding claim 1, in Figures 1 and 5, Yoshimura discloses a component carrier, comprising: an inorganic layer structure (14, paragraph [0027]; Figure 1) having a first main surface (top surface of layer 14) and a second main surface (bottom surface of layer 14); a first electrically insulating layer structure (15) applied on the first main surface of the inorganic layer structure; a first electrically conductive layer structure (26) applied on or above the first electrically insulating layer structure; and at least one inner hole (17) extending through the inorganic layer structure and at least partly through the first electrically insulating layer structure; wherein the at least one inner hole is, along its axis, at least partly covered by a plugging material (43, 18, Figure 5; paragraph [0042]), being different from the first electrically conductive layer structure (Figure 1; layers 43/18 and 26 are different layers), so that the plugging material contacts a lateral side of the inorganic layer structure and a lateral side of the first electrically insulating layer structure (Figures 1 and 5), wherein the plugging material is configured to define a hollow space (Figure 5) containing a conductive material (25, Figure 1) and/or a component. Regarding claim 2, Yoshimura discloses wherein the plugging material does not contact a lateral side of the first electrically conductive layer structure and/or does not extend up to an upper surface of the first electrically conductive layer structure (Figure 1). Regarding claim 3, Yoshimura discloses wherein at an interface between the inorganic layer structure and the first electrically insulating layer structure, the at least one inner hole extends straight through the inorganic layer structure and the first electrically insulating layer structure (Figure 1). Regarding claim 4, Yoshimura discloses wherein the first electrically conductive layer structure is directly applied on the first electrically insulating layer structure (Figure 1). Regarding claim 5, Yoshimura discloses wherein the at least one inner hole comprises a conically-shaped lower inner hole segment, a conically-shaped upper inner hole segment joined to the lower inner hole segment, each of the upper inner hole segment and lower inner hole segment having relatively larger and smaller hole diameter portions, the relatively smaller hole diameter portions of the upper and lower inner hole segments being joined together (Figure 1). Regarding claim 6, Yoshimura discloses wherein an outer hole is formed in the plugging material, wherein the outer hole comprises a conically-shaped lower outer hole segment, a conically-shaped upper outer hole segment joined to the lower outer hole segment, each of the upper outer hole segment and lower outer hole segment having relatively larger and smaller diameter portions, the relatively smaller diameter portions of the upper and lower outer hole segments being joined together (Figure 1). Regarding claim 7, Yoshimura discloses wherein an electrically conductive material is filled in the outer hole (Figure 1). Regarding claim 8, Yoshimura discloses wherein the at least one inner hole also extends through the first electrically conductive layer structure (Figure 1). Regarding claim 9, Yoshimura discloses wherein the first electrically insulating layer structure forms or is part of a double-layer structure comprising a lower insulating layer structure which is applied on the inorganic layer structure and an upper insulating layer structure which is applied on the lower insulating layer structure and the at least one inner hole, wherein the plugging material is formed by material of the upper insulating layer structure (Figure 1). Regarding claim 10, Yoshimura discloses wherein the first electrically insulating layer structure and the first electrically conductive layer structure together are formed by a first resin coated copper foil (Figure 1). Regarding claim 11, Yoshimura discloses a second electrically insulating layer structure applied on the second main surface of the inorganic layer structure; and a second electrically conductive layer structure applied on the second electrically insulating layer structure (Figure 1). Regarding claim 12, Yoshimura discloses a first further electrically insulating layer structure applied or laminated on the first electrically conductive layer structure and the at least one inner hole, wherein the first further electrically insulating layer structure forms the plugging material (Figure 1). Regarding claim 13, Yoshimura discloses a first further electrically conductive layer structure applied on the first further electrically insulating layer structure (Figure 1). Regarding claim 14, Yoshimura discloses wherein the plugging material is at least one of: an electrically insulating plugging material; a magnetic paste; a magnetic paste to implement a coiled copper-structure; an inductive material; an insert (Figure 1). Regarding claim 15, Yoshimura discloses wherein a first inner hole and a second inner hole are provided, wherein the first inner hole is, along its axis, at least partly covered by a first plugging material, and the second inner hole is, along its axis, at least partly covered by a second plugging material, wherein the first and second plugging materials are different from each other (Figure 1). Regarding claim 16, Yoshimura discloses wherein the second plugging material is an epoxy resin material (Figure 1). Regarding claim 17, Yoshimura discloses comprising at least one of the following: an outer hole formed in the plugging material, wherein the outer hole is filled by an electrically conductive material; the plugging material defines an outer hole; the plugging material has a planar surface; the plugging material protrudes from the first electrically insulating layer structure; the component carrier comprises registration holes which are filled by the same plugging material or another electrically insulating plugging material or magnetic paste (Figure 1). Regarding claim 18, Yoshimura discloses a support layer or a temporary carrier; a cavity within the inorganic layer structure, the first electrically insulating layer structure and the first electrically conductive layer structure, wherein a bottom of the cavity is defined by the support layer or the temporary carrier; and a component arranged on the bottom within the cavity (Figure 1). Regarding claim 19, Yoshimura discloses wherein the inorganic layer structure is a glass core and/or comprises at least two glass panels which are connected to each other by an intermediate electrically insulating layer structure therebetween (Figure 1). Regarding claim 20, Yoshimura discloses wherein the component carrier has a symmetric layer stackup with respect to the inorganic layer structure, wherein the symmetric layer stackup includes a symmetric arrangement of at least one of the first electrically insulating layer structure, the first electrically conductive layer structure, the at least one inner hole, the first further electrically insulating layer structure and the first further electrically conductive layer structure (Figure 1). Regarding claim 21, Yoshimura discloses at least one of the following features: the component carrier comprises at least one component surface mounted on and/or embedded in the component carrier, wherein the at least one component is selected from a group consisting of an electronic component, an electrically non-conductive and/or electrically conductive inlay, a heat transfer unit, a light guiding element, an optical element, a bridge, an energy harvesting unit, an active electronic component, a passive electronic component, an electronic chip, a storage device, a filter, an integrated circuit, a signal processing component, a power management component, an optoelectronic interface element, a voltage converter, a cryptographic component, a transmitter and/or receiver, an electromechanical transducer, an actuator, a microelectromechanical system, a microprocessor, a capacitor, a resistor, an inductance, an accumulator, a switch, a camera, an antenna, a magnetic element, a further component carrier, and a logic chip; wherein at least one of the electrically conductive layer structures of the component carrier comprises at least one of the group consisting of copper, aluminum, nickel, silver, gold, palladium, magnesium and tungsten; wherein at least one of the electrically insulating layer structure comprises at least one of the group consisting of reinforced or non-reinforced resin, epoxy resin or bismaleimide-triazine resin, FR-4, FR-5, cyanate ester resin, polyphenylene derivate, glass, prepreg material, polyimide, polyamide, liquid crystal polymer, epoxy-based build-up film, polytetrafluoroethylene, a ceramic, and a metal oxide; wherein the component carrier is shaped as a plate; wherein the component carrier is configured as one of the group consisting of a printed circuit board, a substrate, and an interposer; wherein the component carrier is configured as a laminate-type component carrier (Figure 1). Regarding claim 22, in Figures 1 and 5, Yoshimura discloses a method, comprising: providing an inorganic layer structure (14, paragraph [0027]; Figure 1) having a first main surface (top surface of layer 14) and a second main surface (bottom surface of layer 14); applying a first electrically insulating layer structure (15) on the first main surface of the inorganic layer structure; applying a first electrically conductive layer structure (26) on or above the first electrically insulating layer structure; and providing at least one inner hole (17) extending through the inorganic layer structure and the first electrically insulating layer structure (Figures 1 and 5); wherein the at least one inner hole is, along its axis, at least partly covered by a plugging material (43, 18, Figure 5; paragraph [0042]), being different from the first electrically conductive layer structure (Figure 1; layers 43/18 and 26 are different layers), so that the plugging material contacts a lateral side of the inorganic layer structure and a lateral side of the first electrically insulating layer structure (Figures 1 and 5); wherein the plugging material is configured to define a hollow space (Figure 5) containing a conductive material (25, Figure 1) and/or a component. Regarding claim 23, Yoshimura discloses wherein a second electrically insulating layer structure is applied on the second main surface of the inorganic layer structure and a second electrically conductive layer structure is applied on the second electrically insulating layer structure; or a release layer is applied on the second main surface of the inorganic layer structure or on another surface of the component carrier (Figure 1). Regarding claim 24, Yoshimura discloses applying or laminating a first further electrically insulating layer structure on the first electrically conductive layer structure and the at least one inner hole; and forming an outer hole through the first further electrically insulating layer structure corresponding to the at least one inner hole by laser drilling or mechanical drilling or by wet and/or dry etching (Figure 1). Regarding claim 25, Yoshimura discloses forming a component hole in the inorganic layer structure, the first electrically insulating layer structure and the first electrically conductive layer structure; connecting a support layer or a temporary carrier to a stack comprising the inorganic layer structure, the first electrically insulating layer structure and the first electrically conductive layer structure so that a cavity is formed, wherein a bottom of the cavity is defined by the support layer or the temporary carrier; and arranging a component on the bottom within the cavity (Figure 1). Regarding claim 26, Yoshimura discloses wherein the component carrier is formed to have a symmetric layer stackup with respect to the inorganic layer structure, wherein the symmetric layer stackup includes a symmetric provision of at least one of the first electrically insulating layer structure, the first electrically conductive layer structure, the at least one inner hole, the first further electrically insulating layer structure and the first further electrically conductive layer structure (Figure 1). Regarding claim 27, Yoshimura discloses the following substeps: arranging the inorganic layer structure in an insulating frame; arranging the first resin coated copper foil on the first main surface of the inorganic layer structure and the insulating frame; arranging a second resin coated copper foil on the second main surface of the inorganic layer structure and the insulating frame; laminating the first and second resin coated copper foils to obtain an intermediate stack; and trimming the intermediate stack at its circumference (Figure 1). Regarding claim 28, Yoshimura discloses wherein the step of providing the at least one inner hole is performed by laser drilling or mechanical drilling or by wet and/or dry etching (Figure 1). Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TREMESHA W BURNS whose telephone number is (571)270-3391. The examiner can normally be reached Monday-Friday 8am - 4:30 pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached at (571) 272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. TREMESHA W. BURNS Primary Examiner Art Unit 2847 /TREMESHA W BURNS/Primary Examiner, Art Unit 2847
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Prosecution Timeline

Sep 27, 2023
Application Filed
Jun 28, 2025
Non-Final Rejection — §102
Sep 19, 2025
Response Filed
Dec 26, 2025
Final Rejection — §102
Mar 30, 2026
Request for Continued Examination
Apr 09, 2026
Response after Non-Final Action

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
78%
Grant Probability
99%
With Interview (+22.5%)
2y 6m
Median Time to Grant
Moderate
PTA Risk
Based on 873 resolved cases by this examiner. Grant probability derived from career allow rate.

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