DETAILED ACTION
Examiner’s Note
Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182.
Examiner has cited particular paragraphs, columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. See MPEP 2141.02 VI.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Election/Restrictions
Applicant’s election without traverse of Invention II (method of making semiconductor device), species B, reflected in claims 8-16, 21-31 in the reply filed on 03/31/2026 is acknowledged.
Drawings/Specifications
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the below reference sign(s) mentioned in the description:
Specification ¶ [0012] describes, ‘Fig. 1A’, but there is no fig. 1A included in the drawings.
Specification ¶ [0013] describes, ‘Fig. 1B’, but there is no fig. 1B included in the drawings. The reference elements 131a-b, 103 a-b etc. mentioned in ¶ [0013] are not shown in any of the drawings.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 22-26 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 22 recites the limitation "first surface" in line 8, “bonding the vias on first surface of the interposer to the vias on the first surface of the integrated passive device”. There is insufficient antecedent basis for this limitation in the claim. For examination purpose, the limitataion will be considered as “bonding the vias on the first surface of the interposer to the vias on the first surface of the integrated passive device”
Again, claim 22 recites the limitation "the integrated passive device substrate" in line 10, “removing a portion of a second surface of the integrated passive device substrate”. There is insufficient antecedent basis for this limitation in the claim. For examination purpose, the limitataion “integrated passive device” will be replaced by “integrated passive device substrate” in lines 5, 6, 7, 9.
Again, claim 22 recites the limitataion “the through silicon vias” in line 12, “coupling an integrated circuit to the through silicon vias using solder bumps”. There are two sets of “through silicon vias” defined in this claim—one set in the interposer in line 3 and another set in the integrated passive device in line 11. This is not understood which set of through silicon vias are meant in line 12. For examination purpose, the limitataion will be considered as “coupling an integrated circuit to the through silicon vias of the interposer using solder bumps”.
Summing up all the amendments above, claim 22 will be examined as below:
22. A method of manufacturing an electronic circuit, comprising:
forming an interposer comprising the steps of:
forming through silicon vias in the interposer; and
forming vias on a first surface of the interposer;
forming an integrated passive device substrate comprising the steps of:
forming electrical connections in the integrated passive device substrate; and
forming vias on a first surface of the integrated passive device substrate;
bonding the vias on the first surface of the interposer to the vias on the first surface of the integrated passive device substrate;
removing a portion of a second surface of the integrated passive device substrate;
forming through silicon vias in the second surface of the integrated passive device substrate; and
coupling an integrated circuit to the through silicon vias of the interposer using solder bumps.
As claims 23-26 depend on the above rejected claim 22, they are also being rejected on the same reason.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 9-11, 13-14, 16, 22 and 24 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Haba et al. (US 20130063918 A1, hereinafter Haba‘918).
Regarding independent claim 1, Haba‘918 teaches, “a method of manufacturing an electronic circuit (fig. 1-14; ¶ [0037] - ¶ [0063]) comprising:
forming a first interposer (10B’, see annotated fig. 12) comprising the steps of:
forming through silicon vias (40) in the first interposer; and
forming vias (66, ‘vias’) on a first surface of the first interposer;
forming a second interposer (10A’) comprising the steps of:
forming electrical connections (64, ‘traces’, ¶ [0041]) in the second interposer; and
forming vias (66, ‘vias’) on a first surface of the second interposer;
bonding the vias (66, fig. 13) on first surface of the first interposer (10B’) to the vias (66) on the first surface of the second interposer (10A’);
removing a portion of a second substrate surface (‘expose outside ends 26 and 42’, ¶ [0062], process shown in fig. 8 and post-process device is shown in fig. 5A/fig. 5B/fig. 14) of the second interposer (10A’);
forming through silicon vias in the second substrate surface of the second interposer (silicon vias are formed by removing of a portion of the second substrate surface in previous step or alternately can be done as shown in fig. 7-8 to 130’/130);
coupling an integrated circuit (80, fig. 5A) to the through silicon vias (22) of the second interposer (12) using solder bumps (68)”.
Regarding claim 9, Haba‘918 further teaches, “The method of claim 8, further comprising: after forming through silicon vias (22, fig. 5A) in the second surface of the second interposer (12), removing a portion of a second substrate surface of the first interposer (30); and forming second solder bumps (68) on the second substrate surface of the first interposer (30)”.
Regarding claim 10, Haba‘918 further teaches, “The method of claim 8, wherein forming the second interposer (230, fig. 4C) comprises forming a plurality of capacitors (274, ¶ [0054])”.
Regarding claim 11, Haba‘918 further teaches, “The method of claim 10, wherein the plurality of capacitors comprises embedded deep trench capacitors (274, fig. 4C, ‘appropriately-sized cavity’, ¶ [0056])”.
Regarding claim 13, Haba‘918 further teaches, “The method of claim 10, wherein the plurality of capacitors comprises one or more integrated deep trench capacitors (¶ [0054])”.
PNG
media_image1.png
1380
784
media_image1.png
Greyscale
Regarding claim 14, Haba‘918 further teaches, “The method of claim 10, wherein forming the first interposer further comprises forming a second plurality of capacitors (fig. 4C, as both support portions are same and interchangeable, both can contain passive devices/capacitors)”.
Regarding claim 16, Haba‘918 further teaches, “The method of claim 8, wherein the first and second interposers are silicon interposers (¶ [0010])”.
Regarding independent claim 22, Haba‘918 teaches, “a method of manufacturing an electronic circuit (fig. 1-14; ¶ [0037] - ¶ [0063]) comprising:
forming an interposer (10A’) comprising the steps of:
forming through silicon vias (22) in the interposer (10A’); and
forming vias (66, ‘vias’) on a first surface of the interposer (10A’) (bottom surface);
forming an integrated passive device substrate (10B’ in fig. 12 and 230 in fig. 4C containing passive element 274) comprising the steps of:
forming electrical connections (64) in the integrated passive device substrate; and
forming vias (66 in fig. 12, 266 in fig. 4C, ‘vias’) on a first surface of the integrated passive device (top surface);
bonding the vias on the first surface (bottom surface) of the interposer (10A’) to the vias on the first surface (top surface) of the integrated passive device (10B’);
removing a portion of a second surface (bottom surface) of the integrated passive device substrate (10B’) (‘expose outside ends .. 42’, ¶ [0062], process shown in fig. 8 and post-process device is shown in fig. 5A/fig. 5B/fig. 14);
forming through silicon vias in the second surface of the integrated passive device (silicon vias are formed by removing of a portion from the bottom surface of the integrated passive device substrate in previous step or alternately can be done as shown in fig. 7-8 to 130’/130); and
coupling an integrated circuit to the through silicon vias of the interposer using solder bumps”.
PNG
media_image2.png
290
558
media_image2.png
Greyscale
Regarding claim 24, Haba‘918 further teaches, “The method of claim 22, wherein the interposer is a silicon interposer (¶ [0010])”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 27 and 29 are rejected under 35 U.S.C. 103 as being unpatentable over Haba‘918.
Regarding independent claim 27, Haba‘918 teaches, “a method of manufacturing an electronic circuit (fig. 1-14; ¶ [0037] - ¶ [0063]) comprising:
forming a first interposer (10B’, see annotated fig. 12) comprising the steps of:
forming through silicon vias (40) in the first interposer; and
forming vias (66, ‘vias’) on a first surface of the first interposer;
forming a second interposer (10A’) comprising the steps of:
forming electrical connections (64, ‘traces’, ¶ [0041]) in the second interposer; and
forming vias (66, ‘vias’) on a first surface of the second interposer;
bonding the vias (66, fig. 13) on first surface of the first interposer (10B’) to the vias (66) on the first surface of the second interposer (10A’);
grinding a second surface of the second interposer (10A’) to remove a portion of the second interposer (‘expose outside ends 26’, ¶ [0062], process shown in fig. 8, ‘grinding’, ¶ [0060], and post-process device is shown in fig. 5A/fig. 5B/fig. 14);
((forming through silicon vias in the second surface by etching, depositing conductive material, and chemical mechanical polishing; and))
coupling an integrated circuit (80, fig. 5A) to the through silicon vias (22) of the second interposer (12) using solder bumps (68)”.
Regarding the limitataion, “forming through silicon vias in the second surface by etching, depositing conductive material, and chemical mechanical polishing”, Haba‘918 may not explicitly mention this step in the embodiment described with fig. 12-13. Referring to fig. 12-13, through silicon vias are formed before bonding the two interposers together.
However, another embodiment described with fig. 9-11, wherein through silicon vias are formed after the bonding done of the two interposers together as below:
forming through silicon vias (122) in the second surface by etching, depositing conductive material, and chemical mechanical polishing (fig. 10-11, ¶ [0061] and fig. 8; ¶ [0060])
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of embodiment fig. 12-13 and embodiment fig. 8-11 to form the through silicon vias after bonding according to the teachings of embodiment fig. 8-11 as this provides more flexibility of aligning the two interposers.
Regarding claim 29, Haba‘918 further teaches, “The method of claim 27, wherein the first and second interposers are silicon interposers (¶ [0010])”.
Claims 12, 25 and 30 are rejected under 35 U.S.C. 103 as being unpatentable over Haba‘918 as applied to claims 8, 22 and 27 as above, further in view of Fay‘904.
Regarding claim 12, Haba‘918 teaches all the limitations described in claim 8.
But Haba‘918 is silent upon the provision of wherein the method further comprising covering the integrated circuit and the first and second interposers in a molding compound.
However, Fay‘904 teaches a similar method, wherein the integrated circuit and the first and second interposers are covered in a molding compound (fig. 3C; ¶ [0072]).
Haba‘918 and Fay‘904 are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Haba‘918 with the features of Fay‘904 because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Haba‘918 and Fay‘904 to cover the components of the claimed device with molding compound according to the teachings of Fay‘904 to protect the electrical elements from interference from other neighboring electrical elements.
Regarding claim 25, Haba‘918 modified Fay‘904 with further teaches, “The method of claim 22, further comprising covering the integrated circuit, the interposer, and the integrated passive device in a molding compound (fig. 3C; ¶ [0072])“.
Regarding claim 30, Haba‘918 modified Fay‘904 with further teaches, “The method of claim 27, further comprising covering the integrated circuit and the first and second interposers in a molding compound (fig. 3C; ¶ [0072])“.
Claims 15, 23 and 28 are rejected under 35 U.S.C. 103 as being unpatentable over Haba‘918 as applied to claims 8, 22 and 27 as above, further in view of Fay et al. (US 20230005904 A1, hereinafter Fay‘904).
Regarding claim 15, Haba‘918 teaches all the limitations described in claim 8.
But Haba‘918 is silent upon the provision of wherein the integrated circuit comprises a system on a chip.
However, Fay‘904 teaches a similar method (fig. 3C), wherein the integrated circuit (304) comprises a system on a chip (¶ [0072]).
Haba‘918 and Fay‘904 are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Haba‘918 with the features of Fay‘904 because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Haba‘918 and Fay‘904 to include the SOC according to the teachings of Fay‘904 to use SOC in order to exploit the advantages of SOC e.g., miniature size, power efficiency etc.
Regarding claim 23, Haba‘918 modified Fay‘904 with further teaches, “wherein the integrated circuit comprises a system on a chip (304, fig. 3C; [0072])”.
Regarding claim 28, Haba‘918 modified Fay‘904 with further teaches, “wherein the integrated circuit comprises a system on a chip. (304, fig. 3C; [0072])”.
Claims 21, 26 and 31 are rejected under 35 U.S.C. 103 as being unpatentable over Haba‘918 as applied to claims 8, 22 and 27 as above, further in view of Fay‘904.
Regarding claim 21, Haba‘918 teaches all the limitations described in claim 8.
But Haba‘918 is silent upon the provision of wherein bonding the vias comprises hybrid bonding.
However, Fay‘904 teaches a similar method, wherein bonding the vias comprises hybrid bonding (fig. 3E; ¶ [0076]).
Haba‘918 and Fay‘904 are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Haba‘918 with the features of Fay‘904 because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Haba‘918 and Fay‘904 to use hybrid bonding for bonding the interposers according to the teachings of Fay‘904 to exploit the advantages of hybrid bonding e.g., reliability, high Interconnect Density, design flexibility etc.
Regarding claim 26, Haba‘918 modified Fay‘904 with further teaches, “wherein bonding the vias comprises hybrid bonding (fig. 3E; ¶ [0076])”.
Regarding claim 31, Haba‘918 modified Fay‘904 with further teaches, “wherein bonding the vias comprises hybrid bonding (fig. 3E; ¶ [0076])”.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD M HOQUE whose telephone number is (571)272-6266 and email address is mohammad.hoque@uspto.gov. The examiner can normally be reached 9AM-7PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached on (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MOHAMMAD M HOQUE/Primary Examiner, Art Unit 2817
Prosecution Insights