Prosecution Insights
Last updated: April 19, 2026
Application No. 18/476,058

ELECTRONIC MODULE CONFIGURED FOR THERMAL MANAGEMENT

Final Rejection §103
Filed
Sep 27, 2023
Examiner
REIDA, MOLLY KAY
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Kyosan Electric Manufacturing Co. Ltd.
OA Round
2 (Final)
84%
Grant Probability
Favorable
3-4
OA Rounds
2y 3m
To Grant
86%
With Interview

Examiner Intelligence

Grants 84% — above average
84%
Career Allow Rate
348 granted / 417 resolved
+15.5% vs TC avg
Minimal +2% lift
Without
With
+2.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
31 currently pending
Career history
448
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
46.3%
+6.3% vs TC avg
§102
34.4%
-5.6% vs TC avg
§112
16.0%
-24.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 417 resolved cases

Office Action

§103
DETAILED ACTION Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Rauh et al. (CN116564909A) in view of Bhalla et al. (US Pub. 2003/0178673). Regarding independent claim 19, Rauh teaches an electronic module (Fig. 1; para. 0044+) comprising: a substrate (16; para. 0044); and a plurality of semiconductor dies (12; para. 0044) disposed on the substrate. Rauh teaches wherein each semiconductor die of the plurality of semiconductor dies are preferably transistors such as MOSFET and/or IGBT (para. 0010), but is silent with respect to specific structure(s) of the transistors including wherein each semiconductor die of the plurality of semiconductor dies includes at least one tub comprising a compact active area of the semiconductor die in which a plurality of cells of a power semiconductor device are disposed, and wherein each semiconductor die further includes an inactive region separating the tub from at least one other region of the semiconductor die. Bhalla teaches transistors such as MOSFET and/or IGBT (para. 0002, 0058+) including at least one tub (Fig. 10: 91; para. 0061) comprising a compact active area of the semiconductor die in which a plurality of cells of a power semiconductor device are disposed (the cells being the area between the gate lines – shown more clearly in Figs. 15A, 15B), and wherein each semiconductor die further includes an inactive region (termination region) separating the tub from at least one other region (optional channel stopper area 411 – shown more clearly in Fig. 21A; para. 0079) of the semiconductor die. Bhalla further teaches their device has a high breakdown voltage (para. 0061). Because Rauh is silent with respect a specific structure of the transistor, it would have been obvious to one of ordinary skill in the art at the time of filing to look elsewhere to find a specific structure for the transistor. Bhalla teaches specific structure(s) of semiconductor devices including at least one tub comprising a compact active area of the semiconductor die in which a plurality of cells of a power semiconductor device are disposed, and wherein each semiconductor die further includes an inactive region separating the tub from at least one other region of the semiconductor die. It would have been obvious to one of ordinary skill in the art at the time of filing to choose the claimed structure of Bhalla for the transistors (12) of Rauh with a reasonable expectation of success to arrive at the claimed invention for the purpose of providing a transistor structure with high-breakdown voltage. Re claim 20, the combination of Rauh and Bhalla teaches wherein the power semiconductor device includes a vertical power semiconductor device (Bhalla Fig. 10), and wherein the plurality of semiconductor dies are disposed on the substrate such that center-to-center distances between adjacent tubs are substantially equal (Rauh Fig. 1). Allowable Subject Matter Claims 1 and 3-18 are allowed. Claim 21 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: there is no teaching, suggestion, or motivation from the prior art of record, nor does the prior art of record otherwise make obvious the limitations of “…the driver device being disposed on the substrate between a first semiconductor die of the plurality of semiconductor dies and a second semiconductor die of the plurality of semiconductor dies…”, in combination with the other limitations. Response to Arguments The rejections of claim 1 (and its corresponding dependent claims) has been withdrawn in light of the amendment to claim 1 incorporating previously indicated allowable subject matter into the independent claim 1. These claims (claims 1 and 3-18) have been indicated as allowable. Applicant's remaining arguments with respect to claim 19 have been fully considered but they are not persuasive. While the Examiner agrees that Rauh does not teach “…each semiconductor die…includes at least one tub comprising a compact active area of the semiconductor die in which a plurality of cells of a power semiconductor device are disposed,” and “each semiconductor die further includes an inactive region separating the tub from at least one other region of the semiconductor die.”, Bhalla teaches these features as described above and it would have been obvious to one of ordinary skill in the art at the time of filing to combine the teaching of Rauh and Bhalla to arrive at the claimed invention as described above. Applicant merely asserts that the “Other cited references fail to remedy the deficiencies of Raugh, but fails to explain why/how. Applicant's arguments fail to comply with 37 CFR 1.111(b) because they amount to a general allegation that the claims define a patentable invention without specifically pointing out how the language of the claims patentably distinguishes them from the references. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOLLY KAY REIDA whose telephone number is (571)272-4237. The examiner can normally be reached M-F 8:30-5:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached at (571)272-4237. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MOLLY K REIDA/ Examiner, Art Unit 2899
Read full office action

Prosecution Timeline

Sep 27, 2023
Application Filed
Dec 01, 2025
Non-Final Rejection — §103
Feb 04, 2026
Response Filed
Mar 17, 2026
Final Rejection — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12604647
DISPLAY PANEL AND DISPLAY APPARATUS
2y 5m to grant Granted Apr 14, 2026
Patent 12598736
SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
2y 5m to grant Granted Apr 07, 2026
Patent 12593438
SEMICONDUCTOR MEMORY DEVICES
2y 5m to grant Granted Mar 31, 2026
Patent 12593543
DISPLAY MODULE MANUFACTURING METHOD AND DISPLAY SCREEN
2y 5m to grant Granted Mar 31, 2026
Patent 12593558
DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME
2y 5m to grant Granted Mar 31, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
84%
Grant Probability
86%
With Interview (+2.4%)
2y 3m
Median Time to Grant
Moderate
PTA Risk
Based on 417 resolved cases by this examiner. Grant probability derived from career allow rate.

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