DETAILED ACTION
Claims 1-6, 8-21 are presented for examination.
The present application is being examined under the AIA (America Invents Act) First Inventor to File.
This Office Action is Final.
This action is responsive to the following communication: the response filed on 04-03-2026.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 8, 11-16, 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Publication No. 2017/0149554 (hereinafter Gendler) in view of U.S. Publication No. 2015/0350656 (hereinafter Chung).
As per claims 1, 121, Gendler discloses a method comprising:
switching a first queue (dual mode FIFO for core(s)/GPU; Fig 1 ) on a first end of a data link (interconnect 128; Fig 1) and a second queue (dual mode FIFO for core(s)/GPU; Fig 1 ) on a second end of the data link from a pacing mode to an asynchronous mode; (¶ [0020] states that “the dual mode FIFO 130 can operate in deterministic mode or asynchronous mode.” This suggest that the dual mode FIFO may be transition to with of the two operating modes. Indeed, ¶ [0024] states that dual-mode FIFO may switch from “deterministic mode to asynchronous mode” )
modifying a frequency of a clock associated with the data link; and (¶ [0023] states the invention where “a new clock frequency is sent to and received by one of the cores 122. The command may be sent, for example, from the frequency control unit 120”)
upon modifying the frequency of the clock, returning the first queue and the second queue from the asynchronous mode to the pacing mode. (after “the clock frequency transition is performed” the “the dual mode FIFO 130 is switched back to deterministic mode”. ¶s [0025]-[0026])
Gendler does not distinctly disclose a pacing mode comprising controlling a flow of traffic over the data link based at least in part on bandwidth.
However, Chung discloses a pacing mode comprising controlling a flow of traffic over the data link based at least in part on bandwidth. (abstract states “ dynamically scaling a clock and/or voltage of a video core. The method may include buffering video frames in an input buffer queue and encoding the video frames from the input buffer queue with a video encoder to generate encoded video frames. An input buffer queue is monitored to generate an indication of a fullness of the buffer queue and a high input-threshold level is established for the input buffer queue and a low input-threshold level for the input buffer queue. A clock frequency of the video encoder is increased in response to the indication of the fullness reaching the high input-threshold for the buffer queue and the clock frequency of the video decoder is decreased in response to the indication of the fullness reaching the low input-threshold for the buffer queue.” In other words, the rate flow of data frames from input buffer to output buffer is based on “sufficient space to store to store frame data (from the frame source 102) in the input buffer 106”. ¶ [0025]This limiting constrain is the claimed bandwidth.
It would have been obvious before the effective filing date of the claimed invention to modify the teachings of Gendler and Chung because both references are in the same field of endeavor. Chung’s teaching of adjusting the flow based on queue length would enhance Gendler's system by allowing the system to expedite processing of data such that data is not lost due to overfill, thus improving system processing.
As per claims 2, 13, Gendler as modified discloses a method further comprising exchanging traffic across the data link at a specific time; and (Gendler: The interconnect 128 can also enable the cores 112 to communicate with each other and with the graphics engine 114.; ¶ [0020])
wherein modifying the frequency of the clock comprises modifying the frequency of the clock at the specific time. (Gendler: “a new clock frequency is sent to and received by one of the cores 122. The command may be sent, for example, from the frequency control unit 120”)
As per claims 3, 14, Gendler as modified discloses a method wherein modifying the frequency of the clock comprises reducing the frequency of the clock in response to detecting an activation of a power management feature; and reducing the frequency of the clock while maintaining the data link as active.. (Gendler: ¶ [0033] discloses the system operating in both modes with memory operations (i.e., read/write) not being suspended. ) & (Chung: when the input buffer fullness is low, then a clock of the video encoder 204 can be slowed down to reduce the drain rate from the input buffer queue 206; ¶ [0031])
As per claims 4, 15, Gendler as modified discloses a method further comprising
wherein modifying the frequency of the clock comprises reducing the frequency of the clock in response to detecting the activation of the power management feature. (Gendler: reduce its clock frequency; ¶ [0016])
As per claims 5, 16, Gendler as modified discloses a method further comprising: detecting a deactivation of the power management feature; and (Gendler: frequency control unit that can instruct the core to transition to a new clock frequency.; ¶ [0016]))
increasing the frequency of the clock in response to detecting the deactivation of the power management feature. ( Gendler: increase the frequency; ¶ [0016])
As per claim 18, Gendler as modified discloses a method wherein reducing the frequency of the clock comprises maintaining the data link active as the frequency of the clock is reduced. (Gendler: ¶ [0033] discloses the system operating in both modes with memory operations (i.e., read/write) not being suspended. )
As per claims 8, 19, Gendler as modified discloses a method, wherein: the first queue comprises a first first-in-first-out (FIFO) queue implemented in a data path on a first computing device that represents the first end of the data link; and the second queue comprises a second FIFO queue implemented in a data path on a second computing device that represents the second end of the data link. (Gendler: Fig 1 illustrated plurality of queues for which communication is established)
As per claim 11, Gendler as modified discloses a method wherein: switching the first queue and the second queue to the asynchronous mode comprises switching the first queue and the second queue to the asynchronous mode via firmware implemented on the first end and the second end of the data link or a data link layer implemented across the data link; modifying the frequency of the clock comprises modifying the frequency of the clock via the firmware or the data link layer; and returning the first queue and the second queue from the asynchronous mode to the pacing mode via the firmware or the data link layer. (Gendler: Some embodiments may be implemented with “firmware”; ¶ [0078])
As per claims 6, 17, Gendler as modified discloses a method wherein reducing the frequency of the clock comprises preventing an overflow condition or an underflow condition in at least one of the first queue and the second queue as a result of the activation of the power management feature. (chung: avoid buffer overflow ¶ [0025], abstract, [0032])
Claim(s) 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Publication No. 2017/0149554 (hereinafter Gendler) in view of U.S. Publication No. 2015/0350656 (hereinafter Chung) and further view of U.S. Patent No. 8,255,010 (hereinafter Cheng) and further view of U.S. Publication No. 2021/0365288 (hereinafter Park)..
As per claim 9, Gendler as modified discloses a method wherein modifying the frequency of the clock comprises: setting a first clock implemented on the first computing device to a lower frequency of a reference clock available on the computing device; and setting a second clock associated with an on the computing device to a lower frequency of an additional reference clock available on computing device. (Gendler: “a new clock frequency is sent to and received by one of the cores 122. The command may be sent, for example, from the frequency control unit 120”)
Gendler does not distinctly disclose setting clock frequencies associated with a media access control (MAC) layer.
However, Cheng disclose setting clock frequencies associated with a media access control (MAC) layer. (adjusting the clock frequency and/or the voltage of the device's processor according to the Media Access Control (MAC) layer state are provided. By using a higher clock frequency and/or a higher voltage for a normal operation state with large amounts of data traffic and lower clock frequencies and/or lower voltages for other MAC layer states (e.g., acquisition, network entry, and sleep/idle states), battery power may be conserved,; abstract)
It would have been obvious before the effective filing date of the claimed invention to modify the teachings of Gendler as modified and Cheng because all references are in the same field of endeavor. Cheng’s teaching of adjusting clock speed based on mac layer state would enhance Gendler's system by allowing the system to consume less power, thus improving the battery state for the computer system.
Gendler as modified does not distinctly discloses adjusting the frequency between a fist and second computing device.
However, Park discloses adjusting the frequency between a fist and second computing device. (adjusting frequency for computing device 304 and 306 based on data traffic streaming between them; Fig 3)
It would have been obvious before the effective filing date of the claimed invention to modify the teachings of Gendler as modified and Park because all references are in the same field of endeavor. Park’s teaching of adjusting clock speed between the two device would enhance Gendler's as modified system by allowing the system to accommodate processing between devices in a predictable and sustainable ways, thus enhancing system processing.
As per claim 10, Gendler as modified discloses a method further comprising: confirming that the first FIFO queue has switched to the asynchronous mode prior to modifying the frequency of the first clock; and confirming that the second FIFO queue has switched to the asynchronous mode prior to modifying the frequency of the second clock. (Gendler: acknowledge message; ¶s [0036], [0043])
Claim(s) 21 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Publication No. 2017/0149554 (hereinafter Gendler) in view of U.S. Publication No. 2015/0350656 (hereinafter Chung) and further view of U.S. Publication No. 2023/0385138 (hereinafter Kansal) .
As per claim 21, Gendler does not distinctly discloses a method wherein: the asynchronous mode comprises a first computing device receiving credits and/or allotments for the traffic from a second computing device; and the first computing device controls and/or regulates the flow of the traffic across the data link based at least in part on the credits and/or allotments.
However, Kansal explicitly discloses a method wherein: the asynchronous mode comprises a first computing device receiving credits and/or allotments for the traffic from a second computing device; and the first computing device controls and/or regulates the flow of the traffic across the data link based at least in part on the credits and/or allotments. (¶ [0038])
It would have been obvious before the effective filing date of the claimed invention to modify the teachings of Gendler as modified and Kansal because all references are in the same field of endeavor. Kansal’s teaching of credit flow system would enhance Gendler's as modified system by allowing the system to exchange available resources, thus improving processing within the computer system.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 20, 1, 12 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent No. 8,565,269 (hereinafter Diab) in view of U.S. Publication No. 2017/0149554 (hereinafter Gendler) and in view of U.S. Publication No. 2015/0350656 (hereinafter Chung).
As per claim 20, Diab discloses a computing device comprising:
a communication interface configured to establish a data link with an additional communication interface of a remote device; and (Fig. 1 illustrates link 112 for establishing a network communication between network device 102 and network device 104)
Diab does not distinctly disclose the following:
at least one processor configured to:
switch at least one queue implemented in connection with the communication interface from a pacing mode to an asynchronous mode;
modify a frequency of at least one clock associated with the data link; and
upon modifying the frequency of the at least one clock, returning the at least one queue from the asynchronous mode to the pacing mode.
However, Gendler explicitly discloses the following:
at least one processor configured to:
switch at least one queue implemented in connection with the communication interface from a pacing mode to an asynchronous mode; (¶ [0020] states that “the dual mode FIFO 130 can operate in deterministic mode or asynchronous mode.” This suggest that the dual mode FIFO may be transition to with of the two operating modes. Indeed, ¶ [0024] states that dual-mode FIFO may switch from “deterministic mode to asynchronous mode” )
modify a frequency of at least one clock associated with the data link; and (¶ [0023] states the invention where “a new clock frequency is sent to and received by one of the cores 122. The command may be sent, for example, from the frequency control unit 120”)
upon modifying the frequency of the at least one clock, returning the at least one queue from the asynchronous mode to the pacing mode. (after “the clock frequency transition is performed” the “the dual mode FIFO 130 is switched back to deterministic mode”. ¶s [0025]-[0026])
It would have been obvious before the effective filing date of the claimed invention to modify the teachings of Diab and Gendler because both references are in the same field of endeavor. Gendler’s teaching of dual mode FIFO would enhance Diab's system by allowing the different hardware components to operate with specific clock adjustment, thus improving power management for the computer system.
Gendler as modified does not distinctly disclose a pacing mode comprising controlling a flow of traffic over the data link based at least in part on bandwidth.
However, Chung discloses a pacing mode comprising controlling a flow of traffic over the data link based at least in part on bandwidth. (abstract states “ dynamically scaling a clock and/or voltage of a video core. The method may include buffering video frames in an input buffer queue and encoding the video frames from the input buffer queue with a video encoder to generate encoded video frames. An input buffer queue is monitored to generate an indication of a fullness of the buffer queue and a high input-threshold level is established for the input buffer queue and a low input-threshold level for the input buffer queue. A clock frequency of the video encoder is increased in response to the indication of the fullness reaching the high input-threshold for the buffer queue and the clock frequency of the video decoder is decreased in response to the indication of the fullness reaching the low input-threshold for the buffer queue.” In other words, the rate flow of data frames from input buffer to output buffer is based on “sufficient space to store to store frame data (from the frame source 102) in the input buffer 106”. ¶ [0025]This limiting constrain is the claimed bandwidth.
It would have been obvious before the effective filing date of the claimed invention to modify the teachings of Diab as modified and Chung because all references are in the same field of endeavor. Chung’s teaching of adjusting the flow based on queue length would enhance Diab's as modified system by allowing the system to expedite processing of data such that data is not lost due to overfill, thus improving system processing.
Remarks
Applicant's arguments filed on January 22, 2026 have been considered but are found to be not persuasive as further detailed below.
35 U.S.C. 103 Rejection
A. Independent claim 1
During the After Final remarks, Applicants argues that the cited prior art allegedly fails to discloses the expressions directed to : (i) “switching a first queue on a first end of a data link and a second queue on a second end of a data link” between two different modes and (ii) “modifying a frequency of a clock associated with the data link” as currently recited in the claim 1.
The Office submits that the cited prior explicitly teaches all the expressions recited by independent claim 1. In particular, Fig. 1 of Gender Illustrates a central processing unit 102 having a number circuit cores, where each of the cores is equipped with a buffer (FIFO) that may “enable the cores 112 to communicate with each other” using the data link interconnect 128 ¶ [00200]. According to the same Fig. 1, these buffers are further configured to operate in “dual mode” by allowing at least the frequency control unit to instruct the cores to operate between different frequency bands (i.e, different frequency numbers; ¶ [0018]) when cores are communicating with each other using the data link interconnect 128. Indeed, ¶ [0016] states “ determines an appropriate operating frequency for the various units of the processor 102 including cores 112” based on operating condition of the cores, and in response “the frequency control unit 120 can command the core to reduce its clock frequency, a process known as throttling”. ¶ [0028] further states “FIG. 3 is a block diagram of a dual mode FIFO used to enable rapid frequency transitions. The dual mode FIFO 130 includes a payload FIFO 302 that operates in both clock domains. Data is written to the payload FIFO 302 by the write logic 304 at clock domain A and read out of the payload FIFO 302 by the read multiplexer 306 at clock domain B. Data is written to the payload FIFO 302 at the clock frequency operating in clock domain A and written out of the payload FIFO 302 at the clock frequency operating in clock domain B.” Therefore, Gender explicitly discloses the subject matter directed to (i)“switching a first queue on a first end of a data link and a second queue on a second end of a data link” between two different modes and (ii)“modifying a frequency of a clock associated with the data link” as currently claimed .
B. Independent claim 12
As per independent claim 12, it recites similar features to those recited in claim 1, and therefore, independent claim 12 is rejected for reasons similar to those discussed in independent claim 1.
C. Independent claim 20
As per independent claim 20, Applicant further argues that the prior art further fails to disclose the expression directed to “a communication interface configured to establish a data link with an additional communication interface of a remote device” as currently claimed by independent claim 20.
The Office submits that the cited prior explicitly teaches all the expressions recited by independent claim 20. In particular, Gendler discloses at least data link communication interconnected 128 to communicate with core region 108 and noncore region 110. Fig. 1 illustrates the noncore region 110 to includes noncore components that are external to the core region 108, for example, memory controller 116, interface units 118, and off-chip devices 106. Therefore, these teaching by Gendler explicitly disclose the claimed expression directed to “a communication interface configured to establish a data link with an additional communication interface of a remote device” as currently claimed. Moreover, even if assuming arguendo that Gendler does not distinctly discloses that expression, Diab explicitly discloses link 112 for establishing a network communication between a network device 102 and network device 104 as currently claimed by claim 20.
Therefore, the claimed invention as set forth in the above claims could not be considerable patentable in view of the combination of the cited prior art. Rejections are maintained.
Conclusion
All claims are identical to or patentably indistinct from, or have unity of invention with claims in the application prior to the entry of the submission under 37 CFR 1.114 (that is, restriction (including a lack of unity of invention) would not be proper) and all claims could have been finally rejected on the grounds and art of record in the next Office action if they had been entered in the application prior to entry under 37 CFR 1.114. Accordingly, THIS ACTION IS MADE FINAL even though it is a first action after the filing of a request for continued examination and the submission under 37 CFR 1.114. See MPEP § 706.07(b). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AUREL PRIFTI whose telephone number is (571)270-1743. The examiner can normally be reached on M-F 8 a.m.- 6 p.m..
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kim Ngoc Huynh can be reached on 571-272-4147. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/AUREL PRIFTI/Primary Examiner, Art Unit 2175
Aurel Prifti
Primary Examiner
Art Unit 2175
Tel. (571) 270-1743
Fax (571) 270-2743
aurel.prifti@uspto.gov
1 As per claim 12, the claimed expression directed to “a plurality of computing devices that are communicatively coupled via the data link” is taught by Fig 1 which illustrates computing device such as core(s)/GPU units in communication vis-à-vis interconnect 128.
Prosecution Insights