DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 have been considered but are moot in light of new grounds of rejection made below.
For above mentioned reasons, the rejection is deemed proper and considered final.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 5-6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Aratani et al (US 2005/0226036; hereinafter Aratani).
Regarding claim 1, Fig 1 of Aratami discloses an anti-fuse element (10; Fig 1; ¶ [0132]) comprising:
a first electrode (3; Fig 1; ¶ [0137]);
an insulating layer (4; Fig 39; ¶ [0132]) disposed on the first electrode (3; Fig 39; ¶ [0132]); and
a second electrode (6; Fig 39; ¶ [0132]) disposed on the insulating layer (4; Fig 39; ¶ [0132]), wherein
the insulating layer (4; Fig 39; ¶ [0132]) includes a first region (Central region; Fig 1) and a second region (Outer Region; Fig 1), with a thickness of the first region (Central region; Fig 1) being smaller (Fig 1) than a thickness of the second region (Outer Region; Fig 1), and
an outer edge (Fig 1) of the second electrode (6; Fig 39; ¶ [0132]) is located inward (Fig 1) of an outer edge (Fig 1) of the insulating layer (4; Fig 39; ¶ [0132]) in a top view, and
the first electrode (3; Fig 1; ¶ [0137]) is directly in contact with the insulating layer (4; Fig 39; ¶ [0132]) throughout a portion of the insulation layer (4; Fig 39; ¶ [0132]) that overlaps with the second electrode (6; Fig 39; ¶ [0132]) in the top view.
Regarding claim 2, Fig 1 of Aratami discloses the first region (Central region; Fig 1) of the insulating layer (4; Fig 39; ¶ [0132]) is surrounded by the second region (Outer Region; Fig 1) of the insulating layer (4; Fig 39; ¶ [0132]) in the top view.
Regarding claim 3, Fig 1 of Aratami discloses the second electrode (6; Fig 39; ¶ [0132]) and the insulating layer (4; Fig 39; ¶ [0132]) are partially exposed to an outside (Fig 1).
Regarding claim 5, Fig 1 of Aratami discloses in at least one cross section passing through the first region (Central region; Fig 1), the thickness of the second region (Outer Region; Fig 1) is constant (Fig 1) and a thickness of the second electrode is constant above the second region (Outer Region; Fig 1).
Regarding claim 6, Fig 1 of Aratami discloses the second electrode (6; Fig 39; ¶ [0132]) is configured to be connected to a current supply member only at a portion of the second electrode above the second region of the insulating layer. (¶ [0153])
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4 is rejected under 35 U.S.C. 103 as being unpatentable over Aratani et al (US 2005/0226036; hereinafter Aratani) in view of Suenaga (US 2017/0133578; hereinafter Suenga).
Regarding claim 4, Fig 1 of Aratami discloses the second electrode (6; Fig 39; ¶ [0132]) has a quadrangular shape (Fig 1).
However Aratami does not expressly disclose the second electrode with chamfered comers.
In the same field of endeavor, Fig 2 of Suenga discloses the corners of an electrodes are chamfered (¶ [0033]).
Accordingly it would have been obvious to the person in the ordinary skill in the art before the effective filing date of the invention such that the second electrode are with chamfered corners as the concentration of the electric charge to the corner portions at the time of high voltage application can be dispersed and also the stress can be dispersed and hence breakage caused by crack occurrence can be suppressed (¶ [0031]).
Claim(s) 7-9 are rejected under 35 U.S.C. 103 as being unpatentable over Aratani et al (US 2005/0226036; hereinafter Aratani) in view of Tamaki (US 7659806; hereinafter Tamaki).
Regarding claim 7, Fig 1 of Aratani discloses a conductive substrate (1; Si substrate; Fig 1; ¶ [0162]), wherein the first electrode (3; Fig 1; ¶ [0137]) disposed on the conductive substrate (1; Si substrate; Fig 1; ¶ [0162]).
However Aratani does not expressly disclose an outer edge of the conductive substrate is located outward of an outer edge of the first electrode in the top view.
In the same field of endeavor, Fig 2 of Tamaki discloses a first electrode (2; Fig 2; Col 2; Lines 54) disposed on a substrate (1; Fig 2; line 54) and an outer edge of the substrate is located outward of an outer edge of the first electrode in the top view (Fig 2).
Accordingly it would have been obvious to the person in the ordinary skill in the art before the effective filing date of the invention such that an outer edge of the conductive substrate is located outward of an outer edge of the first electrode in the top view in order to form the substrate with the raised portions on which the electrodes can be formed (Col 2; lines 60-67).
Regarding claim 8, Aratani in view of Tamaki as modified above in claim 7 (Fig 2 of Tamaki in particular) discloses the conductive substrate includes in a thickness direction, a first edge portion flush with the outer edge of the first electrode (2; Fig 2; Col 2; Lines 54 of Tamaki) and a second edge portion located outward of the outer edge of the first electrode in a top view (Fig 2 of Tamaki).
Regarding claim 9, Aratani does not expressly disclose a back surface electrode disposed on the conductive substrate on a side opposite from the first electrode.
In the same field of endeavor, Tamaki discloses a back surface electrode (2; Fig 2; Col 3; lines 9-20) on the substrate (1; Fig 2; line 54) on a side opposite from the first electrode.
Accordingly it would have been obvious to the person in the ordinary skill in the art before the effective filing date of the invention such that a back surface electrode is formed on the substrate in order to form the electrode on the reverse side of the substrate (Col 3; lines 1-5).
Claim(s) 10 is rejected under 35 U.S.C. 103 as being unpatentable over Aratani et al (US 2005/0226036; hereinafter Aratani) in view of Kim et al (US 2022/0285595; hereinafter Kim).
Regarding claim 10, Aratani discloses the anti fuse element according to claim 1 (See the rejection of claim 1).
However Aratani does not expressly disclose a light-emitting device comprising:
a light-emitting element.
In the same field of endeavor, Figs 2 and 7 of Kim discloses a light emitting element (500; Fig 2; ¶ [0073]) and an anti-fuse element (AF1; Fig 7; ¶ [0116]).
Accordingly it would have been obvious to the person in the ordinary skill in the art before the effective filing date of the invention such that a light emitting device comprising a light emitting element and an anti-fuse element in order to form a programmable device that starts in a high-resistance state and is permanently turned into a low-resistance path when a programming voltage is applied (¶ [0007]).
Claim(s) 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Aratani et al (US 2005/0226036; hereinafter Aratani) in view of Kim et al (US 2022/0285595; hereinafter Kim) as applied to claim 10 and further in view of Maeda (US 2021/0400243; hereinafter Maeda).
Regarding claim 11, Aratani in view of Kim as modified above in claim 10 (Kim in particular) discloses the light-emitting element is a semiconductor laser element.
In the same field of endeavor, Maeda discloses a light emitting element may be light emitting diode or semiconductor laser element (¶ [0038]).
Accordingly it would have been obvious to the person in the ordinary skill in the art before the effective filing date of the invention such that a light emitting element can be light emitting diode or semiconductor laser element for the purpose of using well known and suitable device known in the art for forming display device.
Regarding claim 12, Aratani in view of Kim in view of Maeda as modified above in claim 11 discloses the anti-fuse element is disposed in a region a avoiding a virtual straight line including an optical axis of laser light emitted from the semiconductor laser element.
Regarding claim 13, Aratani in view of Kim in view of Maeda (Fig 7 of Maeda in particular) will disclose an additional anti-fuse element (AF2; Fig 7 of Maeda) and an additional semiconductor laser element (Figs 2 and 7 of Maeda) wherein
the anti-fuse element and the semiconductor laser element are connected in parallel to form a first set (Figs 2-7 of Maeda),
the additional anti-fuse element and the additional semiconductor laser element are connected in parallel to form a second set (Figs 2-7 of Maeda), and
the first set and the second set are connected in series (Figs 2-7).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Sanchez et al (US 6156588; This prior art teaches a method of forming an anti-fuse device)
Tani et al (US 2012/0126365; This prior teaches an anti-fuse element)
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RATISHA MEHTA whose telephone number is (571)270-7473. The examiner can normally be reached Monday-Friday: 9:00am - 5:00 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos Feliciano can be reached at 571-272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/RATISHA MEHTA/Primary Examiner, Art Unit 2817
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