Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-2, 5-6, 9-10, 13-16, and 18-20 are rejected under 35 U.S.C. 103 as obvious over Tsai et al. (Pub. No.: US 2022/0293524 A1) in view of Wang et al. (Pub. No. : US 2016/0071818 A1).
Regarding Claim 1, Tsai et al. discloses a manufacturing method of an electronic package, comprising: fixing a plurality of chips to a temporary carrier via a temporary bonding layer (Par. 0045-0048; Figs. 2A-2B - plurality of chips 110 and 120; temporary carrier 202; temporary bonding layer 204); installing at least one bridge element on active surfaces of the adjacent chips, so that the bridge element respectively partially overlaps with the adjacent chips, wherein a plurality of bridging pads of the bridge element are respectively directly bonded to a plurality of first chip pads of the active surfaces of the adjacent chips (Par. 0045-0051; Figs. 2A-2C – bridge element 130; adjacent chips 110 & 120; bridging pads comprising 132p; first chip pads comprising 124p and 114p);
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forming a base dielectric layer covering the temporary bonding layer, the chips, and the bridge element, wherein the base dielectric layer fills a gap between adjacent two of the chips, and a material of the base dielectric layer comprises a silicate composite material or a material suitable for chemical-mechanical polishing and excludes a molding compound (Par. 0045-0057; Figs. 2A-2D – base dielectric layer comprising 150 and 140; the base dielectric layer 140/150 in one embodiment, at least, comprises an inorganic compound such as silicon oxide, silicon oxynitride etc.(and excludes use of a molding compound), which are suitable for chemical-mechanical polishing as proven by the use of this process to thin down or planarize the base dielectric layer (Par. 0034-0035; 0050)); thinning and planarizing the bridge element and the base dielectric layer (Par. 0057; Figs. 2A-2D); forming a plurality of base conductive vias, wherein the base conductive vias respectively pass through the base dielectric layer and are respectively connected to a plurality of second chip pads of the active surfaces of the chips (Par. 0025-0028, 0056-0058; Figs. 2A-2D – base conductive vias 162; second chip pads 122 and 112); forming a redistribution structure on the base dielectric layer and the base conductive vias (Par. 0058-0059; Figs. 2A-2E – redistribution structure 164; base dielectric layer comprising 140 and 150; base conductive vias 162); form a plurality of conductive bumps on the redistribution structure (Par. 0058-0059; Figs. 2A-2E – conductive bumps 166; redistribution structure 164); and removing the temporary bonding layer and the temporary carrier to expose a back surface of each of the chips (Par. 0058-0060; Figs. 2A-2F). Tsai et al. does not explicitly disclose the base dielectric layer is an integrally formed unitary layer that fills a gap between adjacent two of the chips.
However, Wang et al., at least implicitly, teaches forming a base dielectric layer covering the temporary bonding layer, the chips, and the bridge element, wherein the base dielectric layer is an integrally formed unitary layer that fills a gap between adjacent two of the chips (Par. 0132; Fig. 12A – this prior art teaches forming a base
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dielectric layer 1210 covering the temporary bonding layer (not shown but its presence in an earlier processing step implied), the chips 110F_1 and 110F_2, and the bridge element 110N, wherein the base dielectric layer is an integrally formed unitary layer that fills a gap between adjacent two of the chips).
In summary, Tsai et al. teaches first encapsulating the chips 110 and 120 laterally with a first base dielectric layer 140 and then placing the bridge element 130 on top of the chips and forming a second base dielectric layer 150 covering the temporary bonding layer, the chips, and the bridge element (Par. 0034; Figs. 2A-2D). It explicitly teaches that both the first base dielectric layer 140 and the second base dielectric layer 150, at least in some embodiments are formed not of a molding compound. However, as mentioned above, that the base dielectric layer taught by Tsai et al. is not an integrally formed unitary layer. However, the secondary reference Wang et al. teaches a method wherein the base dielectric layer 1210 is an integrally formed unitary layer. However, the base dielectric layer is formed of a molding compound. In short, the two references cited here together teach that the base dielectric layer might be formed of a molding compound or might be formed of a material that excludes molding compound. They also teach that the base dielectric layer might be an integrally formed unitary layer or separately formed of multiple layers. Tsai et al. discloses the claimed invention except for the manufacturing method of the electronic package, wherein the base dielectric layer is an integrally formed unitary layer that fills a gap between adjacent two of the chips. It would have been obvious to one having ordinary skill in the art at the time the invention was filed to adapt the manufacturing method of the electronic package, wherein the base dielectric layer is an integrally formed unitary layer that fills a gap between adjacent two of the chips, since it has been held that forming in one piece an article which has formerly been formed in two pieces and put together involves only routine skill in the art. Howard v. Detroit Stove Works, 150 U.S. 164 (1893).
Regarding Claim 2, Tsai et al., as applied to claim 1, discloses the manufacturing method of the electronic package, wherein each of the chips has a plurality of conductive pillars, the conductive pillars are respectively located on the corresponding second chip pads, in the step of forming the base dielectric layer, the base dielectric layer covers the conductive pillars, and in the step of thinning and planarizing the base dielectric layer, the conductive pillars are shortened and exposed from the base dielectric layer to form the base conductive vias in the step of forming the base conductive vias (Par. 0056-0058; Figs. 2A-2D –second chip pads 122 and 112; pillars comprising 162).
Regarding Claim 3, Tsai et al., as applied to claim 1, discloses the manufacturing method of the electronic package, wherein in the step of thinning and planarizing the bridge element and the base dielectric layer, a thickness of the planarized bridge element is less than a thickness of the chips (Fig. 2D).
Regarding Claim 5, Tsai et al., as applied to claim 1, discloses the manufacturing method of the electronic package, wherein the base dielectric layer comprises a composite material or an inorganic compound suitable for chemical-mechanical polishing (Par. 0034-0035; 0050 – this prior art teaches that the base dielectric layer 140/150 comprises an inorganic compound such as silicon oxide, silicon oxynitride etc. which are suitable for chemical-mechanical polishing as proven by the use of this process to thin down or planarize the base dielectric layer).
Regarding Claim 6, Tsai et al., as applied to claim 1, discloses the manufacturing method of the electronic package, wherein the base dielectric layer does not fill a gap between adjacent two of the bridging pads, and the base dielectric layer does not fill a gap between adjacent two of the first chip pads (Par. 0045-0049; Figs. 2A-2F – base dielectric layer comprising 150 and 140 and it is neither between adjacent two of the bridging pads nor between adjacent two of the first chip pads).
Regarding Claim 9, Tsai et al., as applied to claim 1, discloses the manufacturing method of the electronic package, further comprising: connecting the conductive bumps to a circuit carrier; and connecting a plurality of conductive balls to the circuit carrier (Par. 0038).
Regarding Claim 10, Tsai et al. discloses an electronic package, comprising: a sub-package, comprising: a plurality of chips, arranged on a plane (Par. 0045-0060; Figs. 2A-2F - plurality of chips 110 and 120);
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at least one bridge element, respectively partially overlapping with the adjacent chips, wherein a plurality of bridging pads of the bridge element are respectively directly bonded to a plurality of first chip pads of active surfaces of the adjacent chips (Par. 0045-0060; Figs. 2A-2F – bridge element 130; adjacent chips 110 & 120; bridging pads comprising 132p; first chip pads comprising 124p and 114p); a base dielectric layer, covering the chips and the bridge element, wherein the base dielectric layer fills a gap between adjacent two of the chips and exposes back surfaces of the chips, and a material of the base dielectric layer comprises a silicate composite material or a material suitable for chemical-mechanical polishing and excludes a molding compound (Par. 0045-0057; Figs. 2A-2D – base dielectric layer comprising 150 and 140; the base dielectric layer 140/150 in one embodiment, at least, comprises an inorganic compound such as silicon oxide, silicon oxynitride etc.(and excludes use of a molding compound), which are suitable for chemical-mechanical polishing as proven by the use of this process to thin down or planarize the base dielectric layer (Par. 0034-0035; 0050)); a plurality of base conductive vias, passing through the base dielectric layer and respectively connected to a plurality of second chip pads of the active surfaces of the chips (Par. 0025-0028, 0056-0058; Figs. 2A-2F – base conductive vias 162; second chip pads 122 and 112); a redistribution structure, disposed on the base dielectric layer and the base conductive vias (Par. 0058-0059; Figs. 2A-2F – redistribution structure 164; base dielectric layer comprising 140 and 150; base conductive vias 162);; and a plurality of conductive bumps, disposed on the redistribution structure (Par. 0058-0059; Figs. 2A-2F – conductive bumps 166; redistribution structure 164). Tsai et al. does not explicitly disclose the base dielectric layer is an integrally formed unitary layer that fills a gap between adjacent two of the chips.
However, Wang et al., at least implicitly, teaches forming a base dielectric layer covering the temporary bonding layer, the chips, and the bridge element, wherein the base dielectric layer is an integrally formed unitary layer that fills a gap between adjacent two of the chips (Par. 0132; Fig. 12A – this prior art teaches forming a base
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dielectric layer 1210 covering the temporary bonding layer (not shown but its presence in an earlier processing step implied), the chips 110F_1 and 110F_2, and the bridge element 110N, wherein the base dielectric layer is an integrally formed unitary layer that fills a gap between adjacent two of the chips).
In summary, Tsai et al. teaches first encapsulating the chips 110 and 120 laterally with a first base dielectric layer 140 and then placing the bridge element 130 on top of the chips and forming a second base dielectric layer 150 covering the temporary bonding layer, the chips, and the bridge element (Par. 0034; Figs. 2A-2D). It explicitly teaches that both the first base dielectric layer 140 and the second base dielectric layer 150, at least in some embodiments are formed not of a molding compound. However, as mentioned above, that the base dielectric layer taught by Tsai et al. is not an integrally formed unitary layer. However, the secondary reference Wang et al. teaches a method wherein the base dielectric layer 1210 is an integrally formed unitary layer. However, the base dielectric layer is formed of a molding compound. In short, the two references cited here together teach that the base dielectric layer might be formed of a molding compound or might be formed of a material that excludes molding compound. They also teach that the base dielectric layer might be an integrally formed unitary layer or separately formed of multiple layers. Tsai et al. discloses the claimed invention except for the manufacturing method of the electronic package, wherein the base dielectric layer is an integrally formed unitary layer that fills a gap between adjacent two of the chips. It would have been obvious to one having ordinary skill in the art at the time the invention was filed to adapt the manufacturing method of the electronic package, wherein the base dielectric layer is an integrally formed unitary layer that fills a gap between adjacent two of the chips, since it has been held that forming in one piece an article which has formerly been formed in two pieces and put together involves only routine skill in the art. Howard v. Detroit Stove Works, 150 U.S. 164 (1893).
Regarding Claim 13, Tsai et al., as applied to claim 10, discloses the electronic package, wherein the base dielectric layer comprises a composite material or an inorganic compound suitable for chemical-mechanical polishing (Par. 0034-0035; 0050 – this prior art teaches that the base dielectric layer 140/150 comprises an inorganic compound such as silicon oxide, silicon oxynitride etc. which are suitable for chemical-mechanical polishing as proven by the use of this process to thin down or planarize the base dielectric layer).
Regarding Claim 14, Tsai et al., as applied to claim 10, discloses the electronic package, wherein the base dielectric layer does not fill a gap between adjacent two of the bridging pads, and the base dielectric layer does not fill a gap between adjacent two of the first chip pads (Par. 0045-0049; Figs. 2A-2F – base dielectric layer comprising 150 and 140 and it is neither between adjacent two of the bridging pads nor between adjacent two of the first chip pads).
Regarding Claim 15, Tsai et al., as applied to claim 10, discloses the electronic package, wherein a distribution density of the first chip pads is greater than a distribution density of the second chip pads (Par. 0041).
Regarding Claim 16, Tsai et al., as applied to claim 10, discloses the electronic package, wherein one of the chips is a central processing unit chip, a logic chip, a graphics processing chip, an input/output chip, a memory chip, a base band chip, a radio frequency chip, or an integrated circuit chip with a specific function (Par. 0020).
Regarding Claim 18, Tsai et al., as applied to claim 10, discloses the electronic package, wherein the bridge element is an active element or a passive element (Par. 0029-0030).
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Regarding Claim 19, Tsai et al., as applied to claim 10, discloses the electronic package, further comprising: a circuit carrier, wherein the sub-package is installed on the circuit carrier (Par. 0038).
Regarding Claim 20, Tsai et al., as applied to claim 10, discloses the electronic package, further comprising: a plurality of conductive balls, connected to the circuit carrier (Par. 0038).
Claims 3 and 11 are rejected under 35 U.S.C. 103 as obvious over Tsai et al. (Pub. No.: US 2022/0293524 A1) and Wang et al. (Pub. No. : US 2016/0071818 A1), as applied to claim 1 and claim 10, further in view of Wang et al. (Pub. No. : US 2018/0366436 A1), hereinafter referred to as Wang et al. (‘436”)).
Regarding Claim 3, Tsai et al., as applied to claim 1, discloses the manufacturing method of the electronic package, wherein in the step of thinning and planarizing the bridge element and the base dielectric layer, a thickness of the planarized bridge element is less than a thickness of the chips (Figs. 2A-2F – although not stated explicitly, the drawing shows the thickness of the bridge element to be less than the thickness of the chips). In the alternative, assuming arguendo that Tsai et al. is not emphatic enough regarding the manufacturing method of the electronic package, wherein in the step of thinning and planarizing the bridge element and the base dielectric layer, a thickness of the planarized bridge element is less than a thickness of the chips, Wang et al. (‘436”), at least, implicitly teaches the manufacturing method of the electronic package, wherein in the step of thinning and planarizing the bridge element and the base dielectric layer, a thickness of the planarized bridge element is less than a thickness of the chips (Par. 0037, 0046-0048; Figs. 1-8 – 1-9 – this prior art teaches that the bridge dies could be thinned down to 5 to 10 µm which is substantially thinner than the thickness of most of the normal chips). It would have been obvious to one having ordinary skill in the art at the time the invention was filed to use the teachings of Wang et al. (‘436”) to adapt the manufacturing method of the electronic package, wherein in the step of thinning and planarizing the bridge element and the base dielectric layer, a thickness of the planarized bridge element of Tsai et al. is less than a thickness of the chips in order to reduce overall package thickness.
Regarding Claim 11, Tsai et al., as applied to claim 10, discloses the electronic package, wherein a thickness of the bridge element is less than a thickness of the chips (Figs. 2A-2F – although not stated explicitly, the drawing shows the thickness of the bridge element to be less than the thickness of the chips). In the alternative, assuming arguendo that Tsai et al. is not emphatic enough regarding the electronic package, wherein a thickness of the bridge element is less than a thickness of the chips, Wang et al. (‘436”), at least, implicitly teaches the electronic package, wherein a thickness of the bridge element is less than a thickness of the chips (Par. 0037, 0046-0048; Figs. 1-8 – 1-9 – this prior art teaches that the bridge dies could be thinned down to 5 to 10 µm which is substantially thinner than the thickness of most of the normal chips). It would have been obvious to one having ordinary skill in the art at the time the invention was filed to use the teachings of Wang et al. (‘436”) to adapt the electronic package, wherein a thickness of the bridge element of Tsai et al. is less than a thickness of the chips in order to reduce overall package thickness.
Claims 4 and 12 are rejected under 35 U.S.C. 103 as obvious over Tsai et al. (Pub. No.: US 2022/0293524 A1) and Wang et al. (Pub. No. : US 2016/0071818 A1), as applied to claim 1 and claim 10, further in view of Singh et al. (Patent No. : US 6057035 A).
Regarding Claim 4, Tsai et al., as applied to claim 1, does not explicitly disclose the manufacturing method of the electronic package, wherein the base dielectric layer comprises a silicate nanocomposite material. However, Singh et al., at least implicitly, teaches the manufacturing method of the electronic package, wherein the base dielectric layer comprises a silicate nanocomposite material (abstract, Col. 1, L 48 – Col. 2, L 11 – this prior art teaches a silicate nanocomposite material which has excellent thermal properties and performance characteristics; it also specifically states that these films have applications in diverse fields including in electronic industry). In a nutshell Tsai et al. teaches a base dielectric layer comprising inorganic materials such as silicon oxide, silicon oxynitride etc. (Par. 0034). Singh et al., on the other hand, teaches use of a dielectric layer comprising a silicate nanocomposite material. In other words, use of both an inorganic material-based dielectric layer and the silicate nanocomposite-based dielectric layer have been known to a person of ordinary skill in art before the filing of this invention. Tsai et al. discloses the claimed invention except for the manufacturing method of the electronic package, wherein the base dielectric layer comprises a silicate nanocomposite material. It would have been obvious to one having ordinary skill in the art at the time the invention was filed to adapt the manufacturing method of the electronic package, wherein the base dielectric layer comprises a silicate nanocomposite material, since it has been held that the simple substitution of one known element for another to obtain predictable results is obvious. Furthermore, it has been held to be within the general skill of a worker in the art to be aware that known work in one field of endeavor may prompt variations of it for use in either the same field or a different one based on design incentives or other market forces if the variations would have been predictable to one of ordinary skill in the art. KSR International Co. v Teleflex Inc., 550 U.S.__, __, 82 USPQ2d 1385, 1395-97 (2007)
Regarding Claim 12, Tsai et al., as applied to claim 10, does not explicitly disclose the electronic package, wherein the base dielectric layer comprises a silicate nanocomposite material. However, Singh et al., at least implicitly, teaches the electronic package, wherein the base dielectric layer comprises a silicate nanocomposite material (abstract, Col. 1, L 48 – Col. 2, L 11 – this prior art teaches a silicate nanocomposite material which has excellent thermal properties and performance characteristics; it also specifically states that these films have applications in diverse fields including in electronic industry). In a nutshell Tsai et al. teaches a base dielectric layer comprising inorganic materials such as silicon oxide, silicon oxynitride etc. (Par. 0034). Singh et al., on the other hand, teaches use of a dielectric layer comprising a silicate nanocomposite material. In other words, use of both an inorganic material-based dielectric layer and the silicate nanocomposite-based dielectric layer have been known to a person of ordinary skill in art before the filing of this invention. Tsai et al. discloses the claimed invention except for the electronic package, wherein the base dielectric layer comprises a silicate nanocomposite material. It would have been obvious to one having ordinary skill in the art at the time the invention was filed to adapt the electronic package, wherein the base dielectric layer comprises a silicate nanocomposite material, since it has been held that the simple substitution of one known element for another to obtain predictable results is obvious. Furthermore, it has been held to be within the general skill of a worker in the art to be aware that known work in one field of endeavor may prompt variations of it for use in either the same field or a different one based on design incentives or other market forces if the variations would have been predictable to one of ordinary skill in the art. KSR International Co. v Teleflex Inc., 550 U.S.__, __, 82 USPQ2d 1385, 1395-97 (2007)
Claims 7 and 17 are rejected under 35 U.S.C. 103 as obvious over Tsai et al. (Pub. No.: US 2022/0293524 A1) and Wang et al. (Pub. No. : US 2016/0071818 A1), as applied to claim 1 and claim 10, further in view of Qian et al. (Pub. No. : US 2020/0243448 A1).
Regarding Claim 7, Tsai et al., as applied to claim 1, does not explicitly disclose the manufacturing method of the electronic package, wherein the bridge element has a plurality of bridge conductive vias, and the chips are electrically connected to the redistribution structure via the bridge conductive vias However, Qian et al., at least implicitly, teaches the manufacturing method of the electronic package, wherein the bridge element has a plurality of bridge conductive vias, and the chips are electrically connected to the redistribution structure via the bridge conductive vias (Par. 0039-0047; Fig. 2 – bridge element 212; chips 226, 228; bridge conductive vias can be seen but labeled; redistribution structure comprising 246).. Tsai et al discloses the claimed invention except for the manufacturing method of the electronic package, wherein the bridge element has a plurality of bridge conductive vias, and the chips are electrically connected to the redistribution structure via the bridge conductive vias. It would have been obvious to one having ordinary skill in the art at the time the invention was filed to adapt the manufacturing method of the electronic package, wherein the bridge element has a plurality of bridge conductive vias, and the chips are electrically connected to the redistribution structure via the bridge conductive vias, since it has been held that the provision of adjustability, where needed, involves only routine skill in the art. In re Stevens, 1010 USPQ 284 (CCPA 1954).
Regarding Claim 17, Tsai et al., as applied to claim 10, does not explicitly disclose the electronic package, wherein the bridge element has a plurality of bridge conductive vias, and the chips are electrically connected to the redistribution structure via the bridge conductive vias. However, Qian et al., at least implicitly, teaches the electronic package, wherein the bridge element has a plurality of bridge conductive vias, and the chips are electrically connected to the redistribution structure via the bridge conductive vias (Par. 0039-0047; Fig. 2 – bridge element 212; chips 226, 228; bridge conductive vias can be seen but not labeled; redistribution structure comprising 246). Tsai et al discloses the claimed invention except for the electronic package, wherein the bridge element has a plurality of bridge conductive vias, and the chips are electrically connected to the redistribution structure via the bridge conductive vias. It would have been obvious to one having ordinary skill in the art at the time the invention was filed to adapt the electronic package, wherein the bridge element has a plurality of bridge conductive vias, and the chips are electrically connected to the redistribution structure via the bridge conductive vias, since it has been held that the provision of adjustability, where needed, involves only routine skill in the art. In re Stevens, 1010 USPQ 284 (CCPA 1954).
Claims 8 are rejected under 35 U.S.C. 103 as obvious over Tsai et al. (Pub. No.: US 2022/0293524 A1) and Wang et al. (Pub. No. : US 2016/0071818 A1), as applied to claim 1, further in view of Lin et al. (Pub. No. : US 2022/0223534 A1).
Regarding Claim 8, Tsai et al., as applied to claim 1, does not explicitly disclose the manufacturing method of the electronic package, wherein formation of the base dielectric layer comprises spray coating or spin coating. However, Lin et al., at least implicitly, teaches the manufacturing method of the electronic package, wherein formation of the base dielectric layer comprises spray coating or spin coating (Par. 0031, 0047-0048; Fig. 2F – base dielectric layer comprising layer 106, 108, 116, 28 etc.). Tsai et al discloses the claimed invention except for the manufacturing method of the electronic package, wherein formation of the base dielectric layer comprises spray coating or spin coating. It would have been obvious to one having ordinary skill in the art at the time the invention was filed to adapt the manufacturing method of the electronic package, wherein formation of the base dielectric layer comprises spray coating or spin coating, since it has been held to be within the general skill of a worker in the art to apply a known technique to a known device (method, or product) ready for improvement to yield predictable results is obvious. KSR International Co. v Teleflex Inc., 550 U.S.__, __, 82 USPQ2d 1385, 1395-97 (2007)
Response to Arguments
Applicants’ arguments filed on 07/08/2026 have been fully considered but they are moot because of the new grounds of rejection necessitated by amendments made to the claims.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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07/20/2026
/SYED I GHEYAS/Primary Examiner, Art Unit 2893
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