Office Action Predictor
Last updated: April 15, 2026
Application No. 18/476,390

METHOD FOR FABRICATING SEMICONDUCTOR DEVICE

Non-Final OA §102
Filed
Sep 28, 2023
Examiner
SYLVIA, CHRISTINA A
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Electronics Co., LTD.
OA Round
1 (Non-Final)
88%
Grant Probability
Favorable
1-2
OA Rounds
2y 0m
To Grant
94%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allow Rate
648 granted / 739 resolved
+19.7% vs TC avg
Moderate +7% lift
Without
With
+6.8%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 0m
Avg Prosecution
37 currently pending
Career history
776
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
54.4%
+14.4% vs TC avg
§102
25.0%
-15.0% vs TC avg
§112
19.3%
-20.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 739 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Foreign Priority Receipt is acknowledged of certified copies of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file, as electronically retrieved 11/13/2023 Information Disclosure Statement The information disclosure statement (IDS) submitted on 09/28/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s)1, 3-7, 9-11, 17 and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hwang et al. (PG Pub 2021/0066123; hereinafter Hwang). PNG media_image1.png 459 542 media_image1.png Greyscale Regarding claim 1, refer to Fig. 3a through Fig. 3j (Fig. 3i provided above), Hwang teaches a method for fabricating a semiconductor device (see claim limitations below), the method comprising: forming a mask layer 911,920 on a substrate 211, the mask layer defining a through hole 490 that exposes an upper surface of the substrate (see Fig. 3f), the mask layer comprising a first mask layer 920 and a second mask layer 911, wherein the second mask layer is between the substrate and the first mask layer (see Fig. 3f), and wherein the second mask layer comprises carbon (para [0056]); and forming a liner layer 400 on side walls of the through hole inside the second mask layer (see Fig. 3h). Regarding claim 3, refer to Fig. 3a through Fig. 3j, Hwang teaches a liner layer 400 on the side walls of the through hole 490 inside the second mask layer 911 exposes the upper surface of the substrate 211, and the liner layer is not on an upper surface of the first mask layer and an upper surface of the second mask layer (see Fig. 3i). Regarding claim 4, refer to Fig. 3a through Fig. 3j, Hwang teaches forming a trench (extension of 490 into 211; see Fig. 3i) within the substrate 211, using the mask layer 911,920 and the liner layer 400 as etching masks (see Fig. 3i). Regarding claim 5, refer to Fig. 3a through Fig. 3j, Hwang teaches forming a blocking pattern 511 on the upper surface of the substrate 211 and on the liner layer 400 to partially fill the through hole 490 (see Fig. 3j). Regarding claim 6, refer to Fig. 3a through Fig. 3j (Fig. 3i provided above), Hwang teaches a method for fabricating a semiconductor device (see claim limitations below), the method comprising: forming a pair of line patterns 300 on an insulating film 211, wherein the pair of line patterns extend in a first direction (horizontal); forming a mask layer 911, 920 that defines a through hole 490 that exposes an upper surface of the insulating film (see Fig. 3j), wherein the through hole is between the pair of line patterns in a second direction (vertical direction; see Fig. 3j); forming a liner layer 400 on a first portion of side walls of the through hole (see Fig. 3i); and forming a blocking pattern 511 in the through hole and on the liner layer (see Fig. 3j). Regarding claim 7, refer to Fig. 3a through Fig. 3j, Hwang teaches the mask layer 911,920 comprises a first mask layer 911 and a second mask layer 920, the first mask layer is between the insulating film 211 and the second mask layer (see Fig. 3i), and the first mask layer includes carbon (para [0028]). Regarding claim 9, refer to Fig. 3a through Fig. 3j, Hwang teaches the through hole 490 exposes a portion of the pair of line patterns (end portion of 300; see Fig. 3i). Regarding claim 10, refer to Fig. 3a through Fig. 3j, Hwang teaches the liner layer 400 is not on side walls of the pair of line patterns (400 is not on external sidewalls of 300; see Fig. 3i). Regarding claim 11, refer to Fig. 3a through Fig. 3j, Hwang teaches the liner layer 490 is not on the upper surface of the mask layer 911,920 (see Fig. 3i). Regarding claim 17, refer to Fig. 3a through Fig. 3j, Hwang teaches the blocking pattern 511 includes first side walls (left and right sidewalls), wherein each of the first side walls is opposite to each other in the first direction (horizontal), and each of the first side walls comprises a convex portion (bottom portion). Regarding claim 19, refer to Fig. 3a through Fig. 3j, Hwang teaches forming the mask layer 911,920 further comprises: sequentially forming a first mask layer 911 and a second mask layer 920 on the insulating film 211, forming a photoresist pattern that defines an opening on the second mask layer, and forming the through hole 490, using the photoresist pattern as an etching mask (para [0056]). Prior Art 2. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: a. Kong et al. (PG Pub 2015/0200109) teaches a method for fabricating a semiconductor device. Allowable Subject Matter 3. Claims 2, 8, 12-16 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim 20 is allowed. The following is a statement of reasons for the indication of allowable subject matter: Claim 2 contains allowable subject matter, because the prior art of record, either singularly or in combination, fails to disclose or suggest, in combination with the other elements in claim 2, the liner layer is not on the side walls of the through hole inside the first mask layer. Claim 8 contains allowable subject matter, because the prior art of record, either singularly or in combination, fails to disclose or suggest, in combination with the other elements in claim 8, the first portion of the side walls is adjacent to the first mask layer, and wherein the liner layer is not on a second portion of the side walls of the through hole adjacent to the second mask layer. Claim 12 contains allowable subject matter, because the prior art of record, either singularly or in combination, fails to disclose or suggest, in combination with the other elements in claim 12, forming an insulating material within the through hole and on the upper surface of the mask layer, and etching the insulating material to expose the upper surface of the mask layer. Claim 13 would be allowable, because it depends on allowable claim 12. Claim 14 contains allowable subject matter, because the prior art of record, either singularly or in combination, fails to disclose or suggest, in combination with the other elements in claim 14, removing, in response to forming the blocking pattern, the mask layer and the liner layer to expose the pair of line patterns. Claims 15-16 would be allowable, because they depend on allowable claim 14. Claim 18 contains allowable subject matter, because the prior art of record, either singularly or in combination, fails to disclose or suggest, in combination with the other elements in claim 18, the blocking pattern includes second side walls, wherein each of the second side walls is opposite to each other in the second direction, and the second side walls contact the pair of line patterns. Claim 20 contains allowable subject matter, because the prior art of record, either singularly or in combination, fails to disclose or suggest, in combination with the other elements in claim 20, forming a second insulating film on a first insulating film that comprises a wiring pattern; forming a plurality of line patterns on the second insulating film, wherein the plurality of line patterns extend in a first direction; forming a first mask layer on the second insulating film and the line patterns, wherein the first mask layer comprises carbon; forming a second mask layer on the first mask layer; forming a photoresist pattern on the second mask layer, wherein the photoresist pattern defines an opening; forming a through hole within the first mask layer and the second mask layer, using the photoresist pattern as an etching mask, wherein the through hole exposes the second insulating film; forming a liner layer on a first mask layer and not on the second mask layer; and forming a blocking pattern on the liner layer to at least partially fill the through hole. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Christina A Sylvia whose telephone number is (571)272-7474. The examiner can normally be reached on 8am-4pm (M-F). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached on 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CHRISTINA A SYLVIA/Examiner, Art Unit 2817 /MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
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Prosecution Timeline

Sep 28, 2023
Application Filed
Jan 05, 2026
Non-Final Rejection — §102
Feb 04, 2026
Examiner Interview Summary
Feb 04, 2026
Applicant Interview (Telephonic)
Mar 31, 2026
Response Filed

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
88%
Grant Probability
94%
With Interview (+6.8%)
2y 0m
Median Time to Grant
Low
PTA Risk
Based on 739 resolved cases by this examiner. Grant probability derived from career allow rate.

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