DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-5, 9-13, and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over US Pub. No. 2021/0287120 to Mamidi et al. (“Mamidi”) in view of US Pub. No. 2016/0292313 to Subramaniam et al. (“Subramaniam”).
As to independent claim 9 and similarly recited independent claims 1 and 17, an apparatus for estimating a power, performance, and area (PPA) for a product design (¶ 0042, 0057, Fig. 5, 7. Mamidi teaches an apparatus, method, and CRM for estimating PPA for a product design.), comprising:
a memory device storing instructions (Fig. 7: 704, 726); and a processor configured to execute the instructions stored in the memory device to cause the apparatus to (Fig. 7: 702): place and route design elements in a simulation environment (¶ 0034, 0061: Mamidi teaches computer based placement and routing of circuit design elements in a EDA/simulation design environment.); apply one or more simulation conditions to the design elements (¶ 0032-0034. Mamidi teaches applying simulation/design conditions, including constraints, pre-conditions, layout contexts, flow settings, and multi-corner/multi-mode conditions, to circuit design elements.); obtain a first set of data based on the one or more simulation conditions (¶ 0030, 0032, 0033, 0036. Mamidi teaches obtaining a first set of circuit design/QoR data based on the applied simulation conditions.), (¶ 0035, 0037. Mamidi teaches obtaining a prediction model for predicting circuit design QoR/PPA data.)
predict a new set of data using the prediction model (¶ 0039, 0042, 0044. Mamidi teaches using the trained prediction model to predict a new set of circuit design QoR/PPA data.).
Mamidi trains its ML models using extracted features and corresponding QoR values. Although Mamidi teaches its ML-Delay predictor correlates pre and post-route timing (¶ 0047), Mamidi does not describe first deriving a separately identifiable relationship from the data and then using that relationship as the basis for the prediction model.
Subramaniam is directed to optimizing IC designs (¶ 0003). Subramaniam teaches obtaining a set of PPA data corresponding to different simulation/design conditions (¶ 0040, 0080), obtaining a mathematical relationship, i.e., a ratio/scale factor, from PPA data generated at different design/simulation conditions (¶ 0072, 0082), and obtaining a prediction relationship/model from the derived relationship between PPA data values and using that model to predict a new set of PPA data (¶ 0073, 0083).
It would have been obvious to a PHOSITA to modify Mamidi’s apparatus to incorporate Subramaniam’s relationship based PPA scaling model so that a relationship derived from simulation/design data is obtained and used as a basis of the prediction model. The modification allows Mamidi’s predictor to account for relationships between PPA data obtained under different design, technology, and/or PVT conditions and use those relationships to estimate subsequent PPA data, while preserving Mamidi’s purpose of avoiding unnecessary full design flow runs.
As to claim 10 and similarly recited claims 2 and 18, the apparatus of claim 9, wherein the processor is further configured to execute the instructions stored in the memory device to cause the apparatus to: obtain a second set of data based on the one or more simulation conditions, and a second relationship between the second set of data; and wherein, in obtaining the prediction model, the processor is further configured to execute the instructions stored in the memory device to cause the apparatus to: obtain the prediction model based on the first relationship and the second relationship (Subramaniam: ¶ 0051, 0072, 0081, 0083. Subramaniam teaches obtaining separate sets of PPA data, determining respective technology and PVT scaling relationships from those data, and combining the technology and PVT scaling relationships to generate the predicted trial PPA.).
As to claim 11 and similarly recited claims 3 and 19, the apparatus of claim 9, wherein the product design is a design of an integrated circuit (Mamidi: ¶ 0055, 0057, Subramaniam: ¶ 0003).
As to claim 12 and similarly recited claims 4 and 20, the apparatus of claim 10, wherein obtaining the prediction model comprises determining an equation based on the first relationship and the second relationship (Subramaniam: ¶ 0051, 0062, 0072, 0082, 0083. Subramaniam determines respective scaling relationships by computing ratios between first and second PPA values and combines the technology and PVT scaling relationships to determine an estimated trial PPA. Subramaniam further discloses determining an equation based on performance scaling relationships, including relative speed up Sup and slowdown Sdn, to achieve target performance.).
As to claim 13 and similarly recited claim 5, the apparatus of claim 10, wherein at least one of obtaining the first set of data or obtaining the second set of data comprises obtaining a set of data determined by a power and a speed (¶ 0029, 0041, 0080, 0084. Subramaniam teaches PPA data including power consumption and performance (e.g., operating frequency), and teaches a PPA database containing values for each of power, performance and area at multiple design points. Thus, Subramaniam’s PPA data include both power data and speed data, wherein operating frequency corresponds to the claimed speed.).
Claims 6-8 and 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Mamidi in view of Subramaniam and in further view of Full Chip Power Benefits with Negative Capacitance FET to Samal et al. (“Samal”).
Mamidi in view of Subramaniam teaches the method and apparatus of claims 2 and 10 as disclosed above. Subramaniam teaches obtaining PPA data associated with respective first and second semiconductor technologies and using relationships derived from technology dependent PPA to estimate PPA at a selected design point (¶ 0065-0069, 0072). Subramaniam, however, does not clearly disclose the particular claimed arrangement in which the resulting new set of predicted data is expressly based on a third technology distinct from the first and second technologies (i.e., claims 6 and 14).
Samal teaches PPA related behavior for a distinct third semiconductor technology, specifically 14 nm NCFET technology (Abstract).
It would have been obvious to a PHOSITA to further modify the apparatus of Mamidi, as modified by Subramaniam, so that the new set of predicted data is associated with a third semiconductor technology, such as the new NCFET technology taught by Samal. Doing so would permit estimated PPA data for the third technology to be generated before incurring the computational expense of completing the full place-and-route and signoff analysis for that technology.
As to claim 15 and similarly recited claim 7, the apparatus of claim 14, wherein the processor is further configured to execute the instructions stored in the memory device to cause the apparatus to
evaluate the third technology by comparing a speed at a power under the third technology and a speed at the power under the second technology (Samal teaches “NCFET offers 62% lower power at iso-performance and 44% faster performance at iso-power against the baseline FET” (see Fig. 6 description.), and “[t]he amplification in on-current in NCFET enables 44% faster cell performance at the same power” (see page 4, ¶ 2). Thus, Samal teaches comparing the speed/performance of respective semiconductor technologies at the same power.).
As to claim 16 and similarly recited claim 8, the apparatus of claim 14, wherein the processor is further configured to execute the instructions stored in the memory device to cause the apparatus to: evaluate the third technology by comparing a power at a speed under the third technology and a power at the speed under the second technology (Samal teaches expressly determines that NCFET technology provides 62% lower power than baseline FET technology at iso-performance. See Fig. 6 description.).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Examiner SURESH MEMULA whose telephone number is (571)272-8046, and any inquiry for a formal Applicant initiated interview must be requested via a PTOL-413A form and faxed to the Examiner's personal fax phone number: (571) 273-8046. Furthermore, Applicant is invited to contact the Examiner via email (suresh.memula@uspto.gov) on the condition the communication is pursuant to and in accordance with MPEP §502.03 and §713.01. The Examiner can normally be reached Monday-Thursday: 9am-6pm. If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s supervisor, Jack Chiang, can be reached on 571-272-7483. The fax phone number for the organization where this application or proceeding is assigned (i.e., central fax phone number) is 571-273-8300.
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/SURESH MEMULA/Primary Examiner, Art Unit 2851
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