Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Status of the Claims
Applicant’s election, without traverse, of Group I, claims 1-9, in the reply filed on December 03rd, 2025 is acknowledged. Non-elected invention, claims 10-20 have been withdrawn from consideration. Claims 1-20 are pending.
Action on merits of Group I, claims 1-9 as follows.
Priority
Receipt is acknowledged of certified copies of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on September 28th, 2023 has been considered by the examiner.
Drawings
The drawings filed on 09/28/2023 are acceptable.
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1-5 are rejected under 35 U.S.C. 103 as being unpatentable over Guo (US 2022/0068796, hereinafter as Guo ‘796) in view of Son (US 2018/0151587, hereinafter as Son ‘587).
Regarding Claim 1, Guo ‘796 teaches a semiconductor device, comprising:
a peripheral circuit structure (Fig. 5A, (505); [0055]);
a first capacitor electrode (525-1 (L); [0056]) on the peripheral circuit structure;
an electrode insulating layer (530; [0056]) that at least partially surrounds the first capacitor electrode;
a gate stack (512; [0055]) on the source structure;
a staircase insulating layer (530; [0056]) on the gate stack and the electrode insulating layer;
a second capacitor electrode (525-1 (U); [0056]) on the first capacitor electrode and that extends through the staircase insulating layer (530); and
a penetration via (525-2) that extends through the staircase insulating layer and the electrode insulating layer (130).
Thus, Guo ‘796 is shown to teach all the features of the claim with the exception of explicitly the limitations: “a source structure on the peripheral circuit structure; a memory channel structure that extends through the gate stack”.
Son ‘587 teaches a source structure (Fig. 2, (LSP); [0032]) on the peripheral circuit structure (ACT; [0043]); a memory channel structure (VL; [0035]) that extends through the gate stack (ST; [0046]).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Guo ‘796 by having a source structure on the peripheral circuit structure; a memory channel structure that extends through the gate stack for the purpose of providing semiconductor devices having high operating speeds and/or excellent reliability (see para. [0004]) as suggested by Son ‘587.
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Fig. 5A (Guo ‘796_Annotated)
Regarding Claim 2, Son ‘587 teaches the first capacitor electrode (Fig. 5, (20b); [0047]) at least partially surrounds the penetration via (20a; [0047]).
Regarding Claim 3, Son ‘587 teaches the second capacitor electrode (30b; [0052]) at least partially surrounds the penetration via (20a; [0047]).
Regarding Claim 4, Son ‘587 teaches the source structure comprises a first source layer (LSP) on the peripheral circuit structure (ACT) and a second source layer (USP) on the first source layer (see Fig. 5), the memory channel structure (DS; [0033]) comprises a channel layer and a memory layer that at least partially surrounds the channel layer, and the second source layer (USP) extends through the memory layer and contacts the channel layer;
Thus, Guo ‘796 and Son ‘587 are shown to teach all the features of the claim with the exception of explicitly the limitations: “the first capacitor electrode and the electrode insulating layer are at a same level as the first source layer”.
However, it has been held to be within the general skill of a worker in the art to select the first capacitor electrode and the electrode insulating layer are at a same level as the first source layer on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. A person of ordinary skills in the art is motivated to have the first capacitor electrode and the electrode insulating layer are at a same level as the first source layer in order to improve the performance of the semiconductor devices.
Regarding Claim 5, Son ‘587 teaches a bottom surface of the first capacitor electrode (20a), a bottom surface of the electrode insulating layer (110), and a bottom surface of the first source layer (LSP) are coplanar with each other (see Fig. 5).
Thus, Guo ‘796 and Son ‘587 are shown to teach all the features of the claim with the exception of explicitly the limitations: “a top surface of the first capacitor electrode, a top surface of the electrode insulating layer, and a top surface of the first source layer are coplanar with each other”.
However, it has been held to be within the general skill of a worker in the art to select a top surface of the first capacitor electrode, a top surface of the electrode insulating layer, and a top surface of the first source layer are coplanar with each other on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. A person of ordinary skills in the art is motivated to have a top surface of the first capacitor electrode, a top surface of the electrode insulating layer, and a top surface of the first source layer are coplanar with each other in order to improve the performance of the semiconductor devices.
Claims 6-8 are rejected under 35 U.S.C. 103 as being unpatentable over Guo ‘796 and Son ‘587 as applied to claim 1 above, and further in view of Park (KR 100588899, hereinafter as Park ‘899).
Regarding Claim 6, Guo ‘796 teaches the second capacitor electrode (525-1U; Fig. 5A)
Guo ‘796 and Son ‘587 are shown to teach all the features of the claim with the exception of explicitly the limitations: “the second capacitor electrode comprises a first portion in the first capacitor electrode and a second portion on the first portion”.
Park ‘899 teaches the second electrode (180; pp.4) comprises a first portion in the first electrode (150; pp. 4) and a second portion on the first portion (see Fig. 2C).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Guo ‘796 and Son ‘587 by having the electrode comprises a first portion in the first electrode and a second portion on the first portion in order to prevent the diffusion of copper (see pp. 4) as suggested by Park ‘899.
Regarding Claim 7, Park ‘899 teaches a width of the first portion of the second capacitor electrode (180) is less than a width of the second portion of the second capacitor electrode (see Fig. 2c).
Regarding Claim 8, Guo ‘796 teaches a third portion (MET0) on the second portion of the second capacitor electrode (525-1U).
Guo ‘796’, Son ‘587 and Park ‘899 are shown to teach all the features of the claim with the exception of explicitly the limitations: “a width of the third portion of the second capacitor electrode is less than a width of the second portion of the second capacitor electrode”.
However, it has been held to be within the general skill of a worker in the art to select a width of the third portion of the second capacitor electrode is less than a width of the second portion of the second capacitor electrode on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. A person of ordinary skills in the art is motivated to have a width of the third portion of the second capacitor electrode is less than a width of the second portion of the second capacitor electrode in order to improve the performance of the semiconductor devices.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Guo ‘796 and Son ‘587 as applied to claim 1 above, and further in view of Lee (KR 20220092822, hereinafter as Lee ‘822).
Regarding Claim 9, Guo ‘796 teaches a transistor (818; see para. [0055] and [0071]); and a second peripheral conductive line (CON2) electrically connected to the penetration via (525-2).
Guo ‘796’ and Son ‘587 are shown to teach all the features of the claim with the exception of explicitly the limitations: “a first peripheral conductive line electrically connected to the transistor; a connection via electrically connecting the first peripheral conductive line to the first capacitor electrode”.
Lee ‘822 teaches a first peripheral conductive line (Fig. 1, (261); [0054]) electrically connected to the transistor (see Fig. 1); a connection via (263) electrically connecting the first peripheral conductive line to the first capacitor electrode (266).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Guo ‘796 and Son ‘587 by having a first peripheral conductive line electrically connected to the transistor; a connection via electrically connecting the first peripheral conductive line to the first capacitor electrode in order to improve electrical characteristics and mass production (see para. [0011]) as suggested by Lee ‘822.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The following patents are cited to further show the state of the art with respect to semiconductor devices:
Chen et al. (US 2022/0367505)
Kwon et al. (US 2020/0321349 A1)
For applicant’s benefit portions of the cited reference(s) have been cited to aid in the review of the rejection(s). While every attempt has been made to be thorough and consistent within the rejection it is noted that the PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS. See MPEP 2141.02 VI.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DZUNG T TRAN whose telephone number is (571) 270-3911. The examiner can normally be reached on M-F 8 AM-5PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached on (571) 272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DZUNG TRAN/
Primary Examiner, Art Unit 2893