DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s amendment dated 03/13/2026, in which claims 9, 22-56 were cancelled, has been entered.
Election/Restrictions
Applicant's election with traverse of species 1, Fig. 3A, 3B in the reply filed on 03/13/2026 is acknowledged. The traversal is on the ground(s) that “The Election Requirement Fails to Show that the Identified Species are Independent and Distinct” and “A Showing of Serious Burden Has Not Been Made”. This is not found persuasive because of the following reasons:
First, Applicant’s assertion that “The statute requires, as a basis for legally permissible restriction, that the subject matter of respective claims be both independent and distinct. Neither criterion alone is sufficient. Both must be present in order for the species election requirement to be proper under the 35 U.S.C. § 121” is incorrect.
“If section 121 of the 1952 Act were intended to direct the Director never to approve division between dependent inventions, the word "independent" would clearly have been used alone. If the Director has authority or discretion to restrict independent inventions only, then restriction would be improper as between dependent inventions, e.g., the examples used for purpose of illustration above. Such was clearly not the intent of Congress. Nothing in the language of the statute and nothing in the hearings of the committees indicate any intent to change the substantive law on this subject. On the contrary, joinder of the term "distinct" with the term "independent", indicates lack of such intent. The law has long been established that dependent inventions (frequently termed related inventions) such as used for illustration above may be properly divided if they are, in fact, "distinct" inventions, even though dependent”. MPEP 802.01
Second, the restriction requirement stated “There is a serious search and/or examination burden for the patentably distinct species as set forth above because at least (one) of the following reason(s) apply:
• the species or groupings of patentably indistinct species have acquired a separate status in the art in view of their different classification;
• the species or groupings of patentably indistinct species have acquired a separate status in the art due to their recognized divergent subject matter; and/or
• the species or groupings of patentably indistinct species require a different field of search (e.g., searching different classes/subclasses or electronic resources, or employing different search strategies or search queries); and/or
• non-prior art issues under 35 U.S.C. 101, pre-AIA 35 U.S.C. 112, first paragraph, and/or 35 U.S.C. 112(a) are relevant to one species or grouping of patentably indistinct species that are not relevant to the other species or grouping(s) of patentably indistinct species; and/or
• prior art applied to one species or grouping of patentably indistinct species that cannot be applied to the other species or grouping(s) of patentably indistinct species.”
Therefore, only one reason is needed to show a serious search and/or examination burden. Clearly, the species or groupings of patentably indistinct species require a different field of search (e.g., searching different classes/subclasses or electronic resources, or employing different search strategies or search queries).
“Examiners must provide reasons and/or examples to support conclusions, but need not cite documents to support the restriction requirement in most cases”. See also MPEP 803 II.
Once the examiner sets out prima facie case, the burden shifts to the Applicant to provide evidence of contrary. Until now, Applicant has not provided any evidence to show that there are no serious search and/or examination burden. Applicant has not provided any evidence to show that the species would not require different field of search and would not require employing different search strategies or search queries. Applicant also has not provided any prior art that can be applied to all species. Applicant is reminded that if Applicant is aware of a prior art that reads on all identified species, Applicant has a duty to disclose to the Office. See 37 CFR 1.56.
Overall, Applicant’s arguments are not persuasive. The requirement is still deemed proper and is therefore made FINAL.
Accordingly, claims 16, 18-21 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected species, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-8, 10-15, 17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1 and claim 10, claim 1 and claim 10 each recites the limitation "the second JFET region". There is insufficient antecedent basis for this limitation in the claim.
For the purpose of this Action, the above limitation will be interpreted and examined as --the second JFET sub-region--.
Claims depending from the rejected claims noted above are rejected at least on the same basis as the claim(s) from which the dependent claims depend.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8, 10-15, 17 are rejected under 35 U.S.C. 103 as being unpatentable over Potera (US Pat. 11631762) in view of Kumagai et al. (US Pub. 20150162432).
Regarding claim 1, Potera discloses in Fig. 2 a semiconductor device, comprising:
a semiconductor layer structure [35] that includes a drift layer having a first conductivity type [n type];
a JFET region [43 and 37a, b] that has the first conductivity type [n type] in the upper portion of the drift layer [35];
a plurality of well regions [36a, b] having a second conductivity type [p type] in an upper portion of the drift layer [35]; and
a plurality of source regions [42a,b] having the first conductivity type [n type], where each source region [42a,b] is within a respective one of the well regions [36a,b], wherein the JFET region [43 and 37a,b] comprises a plurality of spaced-apart first JFET sub-regions [37a, b] that each has a first doping concentration [N+] and a second JFET sub-region [43] that has a second doping concentration [N] that is lower than the first doping concentration [N+].
Potera fails to disclose
each well region forming a respective island within the JFET region when viewed in plan view;
the second JFET sub-region extending around at least one of the first JFET sub-regions when viewed in plan view.
Kumagai et al. discloses in Fig. 12, paragraph [0075]
each well region [74b] forming a respective island within the JFET region [72a and 71] when viewed in plan view;
the second JFET sub-region [72a] extending around at least one of the first JFET sub-regions [71] when viewed in plan view.
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It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Kumagai et al. into the method of Potera to include each well region forming a respective island within the JFET region when viewed in plan view; the second JFET sub-region extending around at least one of the first JFET sub-regions when viewed in plan view. The ordinary artisan would have been motivated to modify Potera in the above manner for the purpose of providing suitable plan view of the first JFET sub-region, the second JFET sub-region and the well region to allow the effective resistance of the drift region to decrease and then permits the on-state resistance to decrease [paragraph [0056], [0074]-[0076] of Kumagai et al.].
Regarding claims 2 and 11, Potera discloses in Fig. 2
wherein the first JFET sub- regions [37a, b] comprise implanted regions and the second JFET sub-region [43] comprises an un-implanted region.
Regarding claims 3-8, 12-15, 17, Kumagai et al. discloses in Fig. 12
wherein the plurality of well regions [74b] are arranged in columns,
wherein the well regions [74b] in adjacent columns are offset from each other in a column direction;
wherein each well region [74b] has a hexagonal shape when viewed in plan view;
wherein each first JFET sub- region [71] has an annular hexagonal shape when viewed in plan view;
wherein each first JFET sub- region [71] surrounds a respective one of the well regions [74b] when viewed in plan view;
wherein each first JFET sub- region [71] is positioned between a respective one of the well regions [74b] and the second JFET sub- region [72a] when the semiconductor device is viewed in plan view;
wherein the second JFET sub- region [72a] comprises a continuous region that surrounds each of the first JFET sub-regions [71].
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Regarding claim 10, Potera discloses in Fig. 2 a semiconductor device, comprising:
a semiconductor layer structure [35] that includes a drift layer having a first conductivity type [n type];
a JFET region [43 and 37a, b] that has the first conductivity type [n type] in the upper portion of the drift layer [35];
a plurality of well regions [36a, b] having a second conductivity type [p type] in an upper portion of the drift layer [35];
a plurality of source regions [42a,b] having the first conductivity type [n type], where each source region [42a,b] is within a respective one of the well regions [36a,b],
wherein the JFET region [43 and 37a,b] comprises a plurality of spaced-apart first JFET sub-regions [37a, b] that each has a first doping concentration [N+] and a second JFET sub-region [43] that has a second doping concentration [N] that is lower than the first doping concentration [N+].
Potera fails to disclose
each well region forming a respective island within the JFET region;
the second JFET sub-region extending around at least one of the first JFET sub-regions.
Kumagai et al. discloses in Fig. 12, paragraph [0075]
each well region [74b] forming a respective island within the JFET region [72a and 71];
the second JFET sub-region [72a] extending around at least one of the first JFET sub-regions [71].
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It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Kumagai et al. into the method of Potera to include each well region forming a respective island within the JFET region; the second JFET sub-region extending around at least one of the first JFET sub-regions. The ordinary artisan would have been motivated to modify Potera in the above manner for the purpose of providing suitable plan view of the first JFET sub-region, the second JFET sub-region and the well region to allow the effective resistance of the drift region to decrease and then permits the on-state resistance to decrease [paragraph [0056], [0074]-[0076] of Kumagai et al.].
Claims 1-8, 10-15, 17 are rejected under 35 U.S.C. 103 as being unpatentable over Kumagai et al. (US Pub. 20150162432).
Regarding claim 1, Kumagai et al. discloses in Fig. 1 a semiconductor device, comprising:
a semiconductor layer structure [2] that includes a drift layer having a first conductivity type [n type];
a JFET region [2a and 11] that has the first conductivity type [n type] in the upper portion of the drift layer [2];
a plurality of well regions [4 and 3] having a second conductivity type [p type] in an upper portion of the drift layer [2]; and
a plurality of source regions [5] having the first conductivity type [n type], where each source region [5] is within a respective one of the well regions [4 and 3], wherein the JFET region [2a and 11] comprises a plurality of spaced-apart first JFET sub-regions [11] that each has a first doping concentration [N+] and a second JFET sub-region [2a] that has a second doping concentration [N] that is lower than the first doping concentration [N+].
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Kumagai et al. fails to disclose in embodiment of Fig. 1
each well region forming a respective island within the JFET region when viewed in plan view;
the second JFET sub-region extending around at least one of the first JFET sub-regions when viewed in plan view.
Kumagai et al. discloses in Fig. 12, paragraph [0075]
each well region [74b] forming a respective island within the JFET region [72a and 71] when viewed in plan view;
the second JFET sub-region [72a] extending around at least one of the first JFET sub-regions [71] when viewed in plan view.
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It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Fig. 12 of Kumagai et al. to include each well region forming a respective island within the JFET region when viewed in plan view; the second JFET sub-region extending around at least one of the first JFET sub-regions when viewed in plan view to providing suitable plan view of the first JFET sub-region, the second JFET sub-region and the well region to allow the effective resistance of the drift region to decrease and then permits the on-state resistance to decrease [paragraph [0056], [0074]-[0076] of Kumagai et al.].
Regarding claims 2-8, 11-15, 17, Kumagai et al. discloses in Fig. 1, Fig. 12
wherein the first JFET sub- regions [11] comprise implanted regions and the second JFET sub-region [2a] comprises an un-implanted region.
wherein the plurality of well regions [74b] are arranged in columns,
wherein the well regions [74b] in adjacent columns are offset from each other in a column direction;
wherein each well region [74b] has a hexagonal shape when viewed in plan view;
wherein each first JFET sub- region [71] has an annular hexagonal shape when viewed in plan view;
wherein each first JFET sub- region [71] surrounds a respective one of the well regions [74b] when viewed in plan view;
wherein each first JFET sub- region [71] is positioned between a respective one of the well regions [74b] and the second JFET sub- region [72a] when the semiconductor device is viewed in plan view;
wherein the second JFET sub- region [72a] comprises a continuous region that surrounds each of the first JFET sub-regions [71].
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Regarding claim 10, Regarding claim 1, Kumagai et al. discloses in Fig. 1 a semiconductor device, comprising:
a semiconductor layer structure [2] that includes a drift layer having a first conductivity type [n type];
a JFET region [2a and 11] that has the first conductivity type [n type] in the upper portion of the drift layer [2];
a plurality of well regions [4 and 3] having a second conductivity type [p type] in an upper portion of the drift layer [2]; and
a plurality of source regions [5] having the first conductivity type [n type], where each source region [5] is within a respective one of the well regions [4 and 3], wherein the JFET region [2a and 11] comprises a plurality of spaced-apart first JFET sub-regions [11] that each has a first doping concentration [N+] and a second JFET sub-region [2a] that has a second doping concentration [N] that is lower than the first doping concentration [N+].
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Kumagai et al. fails to disclose in embodiment of Fig. 1
each well region forming a respective island within the JFET region;
the second JFET sub-region extending around at least one of the first JFET sub-regions.
Kumagai et al. discloses in Fig. 12, paragraph [0075]
each well region [74b] forming a respective island within the JFET region [72a and 71];
the second JFET sub-region [72a] extending around at least one of the first JFET sub-regions [71].
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It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Fig. 12 of Kumagai et al. to include each well region forming a respective island within the JFET region; the second JFET sub-region extending around at least one of the first JFET sub-regions to providing suitable plan view of the first JFET sub-region, the second JFET sub-region and the well region to allow the effective resistance of the drift region to decrease and then permits the on-state resistance to decrease [paragraph [0056], [0074]-[0076] of Kumagai et al.].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The cited art discloses similar materials, devices and methods.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SOPHIA T NGUYEN whose telephone number is (571)272-1686. The examiner can normally be reached 9:00am -5:00 pm, Monday-Friday.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, BRITT D HANLEY can be reached at (571)270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SOPHIA T NGUYEN/Primary Examiner, Art Unit 2893
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