DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s amendment dated 06/26/2026, in which claims 9, 18-56 were cancelled, claim 16 was withdrawn, claims 57-60 were added, has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8, 10-15, 17, 57-60 are rejected under 35 U.S.C. 103 as being unpatentable over Potera (US Pat. 11631762) in view of Kumagai et al. (US Pub. 20150162432).
Regarding claim 1, Potera discloses in Fig. 2 a semiconductor device, comprising:
a semiconductor layer structure [35] that includes a drift layer having a first conductivity type [n type];
a JFET region [43 and 37a, b] that has the first conductivity type [n type] in an upper portion of the drift layer [35];
a plurality of well regions [36a, b] having a second conductivity type [p type] in the upper portion of the drift layer [35]; and
a plurality of source regions [42a,b] having the first conductivity type [n type], where each source region [42a,b] is within a respective one of the well regions [36a,b], wherein the JFET region [43 and 37a,b] comprises a plurality of spaced-apart first JFET sub-regions [37a, b] that each have a first doping concentration [N+] and a second JFET sub-region [43] that has a second doping concentration [N] that is lower than the first doping concentration [N+].
Potera fails to disclose
each well region forming a respective island within the JFET region when viewed in plan view;
the second JFET sub-region extending around at least one of the first JFET sub-regions when viewed in plan view.
Kumagai et al. discloses in Fig. 12, paragraph [0075]
each well region [74b] forming a respective island within the JFET region [72a and 71] when viewed in plan view;
the second JFET sub-region [72a] extending around at least one of the first JFET sub-regions [71] when viewed in plan view.
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It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Kumagai et al. into the method of Potera to include each well region forming a respective island within the JFET region when viewed in plan view; the second JFET sub-region extending around at least one of the first JFET sub-regions when viewed in plan view. The ordinary artisan would have been motivated to modify Potera in the above manner for the purpose of providing suitable plan view of the first JFET sub-region, the second JFET sub-region and the well region to allow the effective resistance of the drift region to decrease and then permits the on-state resistance to decrease [paragraph [0056], [0074]-[0076] of Kumagai et al.].
Regarding claims 2 and 11, Potera discloses in Fig. 2
wherein the first JFET sub- regions [37a, b] comprise implanted regions and the second JFET sub-region [43] comprises an un-implanted region.
Regarding claims 3-7, 12-15, Kumagai et al. discloses in Fig. 12
wherein the plurality of well regions [74b] are arranged in columns,
wherein the well regions [74b] in adjacent columns are offset from each other in a column direction;
wherein each well region [74b] has a hexagonal shape when viewed in plan view;
wherein each first JFET sub- region [71] has an annular hexagonal shape when viewed in plan view, and
wherein each well region [74b] surrounds a respective one of the source regions when viewed in plan view [Fig. 12, paragraph [0075] “A source contact (not shown), as similar to the second embodiment, has a hexagonal inside diameter narrower slightly than the second high-concentration p+ base region 74b. The periphery of the p+ contact region 76 is exposed around the p+ contact region 76 in the source contact.… the source contact located at the inner part of the high-concentration p+ base region 74b”];
wherein each first JFET sub- region [71] surrounds a channel region [portion of 74b that is visible in plan view] of a respective one of the well regions [74b] when viewed in plan view;
wherein each first JFET sub- region [71] is positioned between a respective one of the well regions [74b] and the second JFET sub- region [72a] when the semiconductor device is viewed in plan view;
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Regarding claim 8, Potera discloses in Fig. 2
wherein the JFET region [43 and 37a, b] is in the upper portion of the drift layer [35] between ones of the well regions [36a, b];
Kumagai et al. discloses in Fig. 12
wherein the JFET region [71 and 72a] is between ones of the well regions [74b];
wherein the second JFET sub- region [72a] comprises a continuous region that surrounds each of the first JFET sub-regions [71].
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Thus, the combination of Potera and Kumagai et al. discloses limitation of claim 8.
Regarding claim 10, Potera discloses in Fig. 2 a semiconductor device, comprising:
a semiconductor layer structure [35] that includes a drift layer having a first conductivity type [n type];
a JFET region [43 and 37a, b] that has the first conductivity type [n type] in an upper portion of the drift layer [35];
a plurality of well regions [36a, b] having a second conductivity type [p type] in the upper portion of the drift layer [35];
a plurality of source regions [42a,b] having the first conductivity type [n type], where each source region [42a,b] is within a respective one of the well regions [36a,b],
wherein the JFET region [43 and 37a,b] comprises a plurality of spaced-apart first JFET sub-regions [37a, b] that each has a first doping concentration [N+] and a second JFET sub-region [43] that has a second doping concentration [N] that is lower than the first doping concentration [N+].
Potera fails to disclose
each well region forming a respective island within the JFET region;
the second JFET sub-region extending around and spaced apart from at least one of the well regions by a respective one of the first JFET sub-regions when viewed in plan view.
Kumagai et al. discloses in Fig. 12, paragraph [0075]
each well region [74b] forming a respective island within the JFET region [72a and 71];
the second JFET sub-region [72a] extending around and spaced apart from at least one of the well regions [74b] by a respective one of the first JFET sub-regions [71] when viewed in plan view.
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It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Kumagai et al. into the method of Potera to include each well region forming a respective island within the JFET region; the second JFET sub-region extending around and spaced apart from at least one of the well regions by a respective one of the first JFET sub-regions when viewed in plan view. The ordinary artisan would have been motivated to modify Potera in the above manner for the purpose of providing suitable plan view of the first JFET sub-region, the second JFET sub-region and the well region to allow the effective resistance of the drift region to decrease and then permits the on-state resistance to decrease [paragraph [0056], [0074]-[0076] of Kumagai et al.].
Regarding claim 17, Kumagai et al. discloses in Fig. 12
wherein the second JFET sub- region [72a] comprises a continuous region that surrounds each of the first JFET sub-regions [71];
and wherein, between an adjacent pair of the well regions [74b], a width of at least one of the first JFET sub-regions [71] is less than a width of the second JFET sub-region [72a].
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Regarding claim 57, Potera discloses in Fig. 2 a semiconductor device, comprising:
a semiconductor layer structure [35] that includes a drift layer having a first conductivity type [n type];
a JFET region [43 and 37a, b] that has the first conductivity type [n type] in an upper portion of the drift layer [35];
a plurality of well regions [36a, b] having a second conductivity type [p type] in the upper portion of the drift layer [35],
a plurality of source regions [42a,b] having the first conductivity type [n type], where each source region [42a,b] is within a respective one of the well regions [36a,b],
wherein the JFET region [43 and 37a,b] comprises a plurality of spaced-apart first JFET sub-regions [37a, b] that each has a first doping concentration [N+] and a second JFET sub-region [43] that has a second doping concentration [N] that is lower than the first doping concentration [N+].
Potera fails to disclose
each well region forming a respective island within the JFET region when viewed in plan view;
wherein at least one of the first JFET sub-regions extends around an outer periphery of a respective one of the well regions when viewed in plan view.
Kumagai et al. discloses in Fig. 12, paragraph [0075]
each well region [74b] forming a respective island within the JFET region [72a and 71] when viewed in plan view;
wherein at least one of the first JFET sub-regions [71] extends around an outer periphery of a respective one of the well regions [74b] when viewed in plan view;
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It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Kumagai et al. into the method of Potera to include each well region forming a respective island within the JFET region when viewed in plan view; wherein at least one of the first JFET sub-regions extends around an outer periphery of a respective one of the well regions when viewed in plan view. The ordinary artisan would have been motivated to modify Potera in the above manner for the purpose of providing suitable plan view of the first JFET sub-region, the second JFET sub-region and the well region to allow the effective resistance of the drift region to decrease and then permits the on-state resistance to decrease [paragraph [0056], [0074]-[0076] of Kumagai et al.].
Regarding claim 58, Potera discloses in Fig. 2
wherein the at least one of the first JFET sub-regions [37a, b] is positioned directly between the respective one of the well regions [36a, b] and the second JFET sub-region [43] when viewed in a cross-section view. Thus, the at least one of the first JFET sub-regions [37a, b] is also positioned directly between the respective one of the well regions [36a, b] and the second JFET sub-region [43] when viewed in plan view.
Regarding claim 59, Kumagai et al. discloses in Fig. 12, paragraph [0074]
wherein each well region [74b] has a hexagonal shape when viewed in plan view.
Regarding claim 60, Potera and Kumagai et al. fails to disclose
wherein the first doping concentration is between 1x1016cm-3 and 2x1017 cm3.
Potera discloses in column 6 “[t]he slope of the electric field is a function of Nj2 (i.e., the doping concentration of sidewall areas 37)… JFET doping of sidewall areas 37 may be selected so as match the JFET resistance of a traditional DMOSFET device at the process center of the traditional design.”
In addition, Applicant has not provided criticality of the claim range. It would have been obvious to modify Potera and Kumagai et al. to provide the first doping concentration is between 1x1016cm3 and 2x1017 cm3. The ordinary artisan would have been motivated to modify Potera and Kumagai et al. in the manner set forth above for at least the purpose of optimization and routine experimentation to obtain desired JFET resistance. The claimed ranges are merely optimizations, and as such are not patentable over the prior art. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). "The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages." Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382.
Claims 1-8, 10-15, 17 are rejected under 35 U.S.C. 103 as being unpatentable over Kumagai et al. (US Pub. 20150162432).
Regarding claim 1, Kumagai et al. discloses in Fig. 1 a semiconductor device, comprising:
a semiconductor layer structure [2] that includes a drift layer having a first conductivity type [n type];
a JFET region [2a and 11] that has the first conductivity type [n type] in an upper portion of the drift layer [2];
a plurality of well regions [4 and 3] having a second conductivity type [p type] in the upper portion of the drift layer [2]; and
a plurality of source regions [5] having the first conductivity type [n type], where each source region [5] is within a respective one of the well regions [4 and 3], wherein the JFET region [2a and 11] comprises a plurality of spaced-apart first JFET sub-regions [11] that each has a first doping concentration [N+] and a second JFET sub-region [2a] that has a second doping concentration [N] that is lower than the first doping concentration [N+].
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Kumagai et al. fails to disclose in embodiment of Fig. 1
each well region forming a respective island within the JFET region when viewed in plan view;
the second JFET sub-region extending around at least one of the first JFET sub-regions when viewed in plan view.
Kumagai et al. discloses in Fig. 12, paragraph [0075]
each well region [74b] forming a respective island within the JFET region [72a and 71] when viewed in plan view;
the second JFET sub-region [72a] extending around at least one of the first JFET sub-regions [71] when viewed in plan view.
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It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Fig. 12 of Kumagai et al. to include each well region forming a respective island within the JFET region when viewed in plan view; the second JFET sub-region extending around at least one of the first JFET sub-regions when viewed in plan view to providing suitable plan view of the first JFET sub-region, the second JFET sub-region and the well region to allow the effective resistance of the drift region to decrease and then permits the on-state resistance to decrease [paragraph [0056], [0074]-[0076] of Kumagai et al.].
Regarding claims 2-7, 11-15, Kumagai et al. discloses in Fig. 1, Fig. 12
wherein the first JFET sub- regions [11] comprise implanted regions and the second JFET sub-region [2a] comprises an un-implanted region.
wherein the plurality of well regions [74b] are arranged in columns,
wherein the well regions [74b] in adjacent columns are offset from each other in a column direction;
wherein each well region [74b] has a hexagonal shape when viewed in plan view;
wherein each first JFET sub- region [71] has an annular hexagonal shape when viewed in plan view;
wherein each first JFET sub- region [71] surrounds a respective one of the well regions [74b] when viewed in plan view;
wherein each first JFET sub- region [71] is positioned between a respective one of the well regions [74b] and the second JFET sub- region [72a] when the semiconductor device is viewed in plan view;
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Regarding claim 8, Kumagai et al. discloses in Fig. 1
wherein the JFET region [2a and 11] is in the upper portion of the drift layer [2] between ones of the well regions [4 and 3];
Kumagai et al. discloses in Fig. 12
wherein the JFET region [71 and 72a] is between ones of the well regions [74b];
wherein the second JFET sub- region [72a] comprises a continuous region that surrounds each of the first JFET sub-regions [71].
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Regarding claim 10, Kumagai et al. discloses in Fig. 1 a semiconductor device, comprising:
a semiconductor layer structure [2] that includes a drift layer having a first conductivity type [n type];
a JFET region [2a and 11] that has the first conductivity type [n type] in the upper portion of the drift layer [2];
a plurality of well regions [4 and 3] having a second conductivity type [p type] in an upper portion of the drift layer [2]; and
a plurality of source regions [5] having the first conductivity type [n type], where each source region [5] is within a respective one of the well regions [4 and 3], wherein the JFET region [2a and 11] comprises a plurality of spaced-apart first JFET sub-regions [11] that each has a first doping concentration [N+] and a second JFET sub-region [2a] that has a second doping concentration [N] that is lower than the first doping concentration [N+].
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Kumagai et al. fails to disclose in embodiment of Fig. 1
each well region forming a respective island within the JFET region;
the second JFET sub-region extending around and spaced apart from at least one of the well regions by a respective one of the first JFET sub-regions when viewed in plan view.
Kumagai et al. discloses in Fig. 12, paragraph [0075]
each well region [74b] forming a respective island within the JFET region [72a and 71];
the second JFET sub-region [72a] extending around and spaced apart from at least one of the well regions [74b] by a respective one of the first JFET sub-regions [71] when viewed in plan view.
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It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Fig. 12 of Kumagai et al. to include each well region forming a respective island within the JFET region; the second JFET sub-region extending around and spaced apart from at least one of the well regions by a respective one of the first JFET sub-regions when viewed in plan view to providing suitable plan view of the first JFET sub-region, the second JFET sub-region and the well region to allow the effective resistance of the drift region to decrease and then permits the on-state resistance to decrease [paragraph [0056], [0074]-[0076] of Kumagai et al.].
Regarding claim 17, Kumagai et al. discloses in Fig. 12
wherein the second JFET sub- region [72a] comprises a continuous region that surrounds each of the first JFET sub-regions [71];
and wherein, between an adjacent pair of the well regions [74b], a width of at least one of the first JFET sub-regions [71] is less than a width of the second JFET sub-region [72a].
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Response to Arguments
Applicant's arguments filed 06/26/2026 have been fully considered but they are not persuasive.
Regarding Applicant’s arguments on page 2 that “the Office Action's reliance on the high-concentration region 71 of Kumagai as corresponding to the claimed "at least one of the first JFET sub-regions" is flawed. In particular, Kumagai identifies region 72a as the JFET region and identifies the high- concentration region 71 as a region distinct from the JFET region 72a. At paragraph [0075], Kumagai describes the high-concentration region 71 as being "located at the inner part of high- concentration p+ base region 74b." Kumagai therefore does not teach or suggest that the high- concentration region 71 is a sub-region of a JFET region, as recited in Claim 1,” Examiner respectfully disagree because per MPEP 2131, “[t]he elements must be arranged as required by the claim, but this is not an ipsissimis verbis test, i.e., identity of terminology is not required. In re Bond, 910 F.2d 831, 15 USPQ2d 1566 (Fed. Cir. 1990)”. In this case, in the rejection, a JFET region [72a and 71] is indicated as a region comprising at least one of high- concentration region 71 and the lower concentration 72a. Below are two examples of a JFET region:
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Regarding Applicant’s arguments that “Applicant therefore respectfully submits that both Kumagai alone and the proposed combination of Potera and Kumagai fail to teach or suggest at least the portion of amended Claim 10 reciting "the second JFET sub-region extending around and spaced apart from at least one of the well regions by a respective one of the first JFET sub-regions when viewed in plan view”, Examiner respectfully disagrees because as stated above, Fig. 12 of Kumagai suggests "the second JFET sub-region extending around and spaced apart from at least one of the well regions by a respective one of the first JFET sub-regions when viewed in plan view”
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In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Overall, Applicant’s arguments are not persuasive. The claims stand rejected and the Action is made FINAL.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SOPHIA T NGUYEN whose telephone number is (571)272-1686. The examiner can normally be reached 9:00am -5:00 pm, Monday-Friday.
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/SOPHIA T NGUYEN/Primary Examiner, Art Unit 2893
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