Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of claims 2-10 in the reply filed on 26 September, 2025 is acknowledged. Claim 1 has been withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention(s)/ species, there being no allowable generic or linking claim.
Information Disclosure Statement
The Information Disclosure Statements (IDS) submitted on 9/28/23 by the applicant have been received and fully considered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 2-17 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claims 2–17 repeatedly recite “scheme #1”, “scheme #2”, … “scheme #9”, but: The claims do not define: structural boundaries of each “scheme”, what required circuit elements for each scheme and how schemes differ functionally rather than by label.
The specification uses “scheme” as an informal design label, not as a claim-defining term.
The term “scheme” (emphasis)is not a recognized term of art defining a specific circuit structure, and the claims do not recite structural elements that distinguish one “scheme” from another. Instead, the claims rely on ordinal labels without specifying how each scheme is implemented, how it differs structurally from other schemes, or what minimum elements are required for each scheme.
As a result, a person of ordinary skill in the art would not be reasonably apprised of the scope of the claimed subject matter, rendering the claims indefinite..
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-17, as best understood (See the 112 Rejection above), are rejected under 35 U.S.C. §103 as being unpatentable over Wang et al.( US 11,526,285) in view of Choi et al. (US 10,643,705).
Examiner’s Note:
A reference must be considered in its entirety, not in isolation.”— In re Wesslau, 353 F.2d 238.
“The test for obviousness is what the combined teachings of the references would have suggested to those of ordinary skill in the art.”
— In re Keller, 642 F.2d 413 (CCPA 1981).
Key Note for the Applicant to consider:
There is no legal requirement that: all limitations appear in one figure, or all limitations be disclosed in one paragraph.
Thus, This Office Action properly relies on the teachings of the references as a whole, not on a rigid, element-by-element figure overlay.
Also, The examiner used “the cited references are relied upon for their combined teachings as understood by a person of ordinary skill in the art. The Office Action does not require a one-to-one correspondence between individual claim limitations and a single figure or paragraph of any reference. Rather, the rejection properly relies on the collective disclosures of the references, which, when combined, render the claimed subject matter obvious under 35 U.S.C. §103.”
Regarding independent claim 2: Claim 2 recites that the RCM performs inference in a parallel mode by activating each row.
Claim 2 is rejected under 35 U.S.C. §103 as being unpatentable over Wang et al.( US 11,526,285) in view of Choi et al. (US 10,643,705).
Wang et al. discloses a fully integrated RRAM-based AI accelerator comprising ratio-based crossbar macros in which process elements are arranged in rows and columns, input voltages are applied to rows via digital-to-analog converters, and output currents are summed along columns and digitized by shared analog-to-digital converters (e.g., see Wang, Figs. 2–4; col. 6, ll. 5–40; col. 8, ll. 10–45). Wang further teaches performing inference operations in parallel by activating multiple rows simultaneously.
Choi et al. further discloses specific processing element configurations for RRAM crossbars, including variants optimized for addition and subtraction operations, and teaches the use of shared ADC resources across multiple columns to reduce area and power consumption (e.g., see Choi, Figs. 3–5; col. 7, ll. 1–30).
A person of ordinary skill in the art would have been motivated to combine the system-level architecture of Wang with the processing-element configurations of Choi to implement a ratio-based crossbar macro capable of parallel inference using shared ADCs, as both references address the same technical problem of efficient neural network computation using RRAM crossbars. The combination represents a predictable use of prior art elements according to their established functions
Claim 3 depends from claim 2 and further recites that the RCM performs inference in a parallel mode by activating each row.
Wang et al. teaches performing inference operations in parallel within an RRAM crossbar by simultaneously activating multiple word lines corresponding to rows of processing elements (e.g., see Wang, Figs. 3–4; col. 8, ll. 15–35). Wang explicitly discloses row-wise activation to compute outputs concurrently across columns. Accordingly, claim 3 is unpatentable under 35 U.S.C. §103 as obvious over Wang.
Claim 4 depends from claim 3 and recites an architecture for addition having size (M×2N) with left and right arrays and an iT1R processing element.
Wang et al. discloses paired crossbar sub-arrays arranged laterally to implement differential and addition-based computation using current summation across columns (e.g., see Wang, Fig. 6; col. 9, ll. 10–30). The use of multiple arrays to support addition operations is therefore taught by Wang. Claim 4 is unpatentable under §103 as obvious over Wang.
Claim 5 depends from claim 3 and recites that the processing elements comprise a one-transistor-one-resistor (1T1R) structure with bit lines, word lines, and source lines collecting summed currents.
Choi et al. explicitly discloses 1T1R processing elements in RRAM crossbar arrays, where word lines control transistor gates, bit lines apply input voltages, and source lines collect summed currents for column outputs (e.g., see Choi, Fig. 4; col. 7, ll. 20–45). Accordingly, claim 5 is unpatentable under §103 as obvious over Choi.
Claim 6 depends from claim 5 and further recites a dual-array architecture where one array is biased with a constant conductance and another array stores synaptic weights.
Wang et al. discloses using reference or bias arrays with fixed conductance values in combination with weight-mapped arrays to perform normalized or ratio-based computation in RRAM crossbars (e.g., see Wang, Fig. 7; col. 10, ll. 5–30).
Therefore, claim 6 is unpatentable under §103 as obvious over Wang.
Claim 7 depends from claim 3 and recites an addition architecture using a single (M×N) array with a 2T2R processing element.
Choi et al. discloses processing elements having two transistors and two resistive memory devices arranged to support differential addition and subtraction operations within a single crossbar array (e.g., see Choi, Fig. 5; col. 8, ll. 1–25). Claim 7 is unpatentable under §103 as obvious over Choi.
Claim 8 depends from claim 3 and recites an addition architecture using a single (M×N) array with a 1T2R processing element.
Choi et al. further teaches 1T2R processing elements in which paired resistive devices are coupled to a single transistor to enable addition and subtraction operations (e.g., see Choi, Fig. 6; col. 8, ll. 30–55).
Accordingly, claim 8 is unpatentable under §103 as obvious over Choi.
Claim 9 depends from claim 8 and recites that one RRAM cell connects to a bit line and another connects to a constant bias voltage.
Wang et al. discloses applying constant bias voltages to selected bit lines in RRAM arrays to support reference-based current summation and normalization (e.g., see Wang, col. 9, ll. 40–55).
Claim 9 is unpatentable under §103 as obvious over Wang.
Claim 10 depends from claim 3 and recites an architecture having a size (2M×N) with upper and lower arrays and a 1T1R processing element.
Wang et al. teaches stacking or duplicating crossbar arrays vertically or logically to expand computational dimensions and support multi-row addition operations (e.g., see Wang, Fig. 8; col. 11, ll. 5–25).
Claim 10 is unpatentable under §103 as obvious over Wang.
Claim 11 depends from claim 3 and recites an addition architecture with a (M×N) array and a 2T2R processing element.
As discussed above with respect to claim 7, Choi et al. expressly discloses 2T2R processing elements used within a single crossbar array to implement addition operations (e.g., see Choi, Fig. 5; col. 8, ll. 1–25).
Claim 11 is unpatentable under §103 as obvious over Choi.
Claim 12 depends from claim 3 and recites a subtraction operation using a single array with a 2T2R processing element.
Choi et al. teaches implementing subtraction operations by differential current comparison using paired resistive elements within a 2T2R processing element (e.g., see Choi, col. 8, ll. 20–40).
Accordingly, claim 12 is unpatentable under §103 as obvious over Choi.
Claim 13 depends from claim 3 and recites a subtraction operation using a single array with a 1T1R processing element.
Wang et al. discloses performing subtraction and differential operations using single-transistor resistive elements combined with reference biases (e.g., see Wang, col. 10, ll. 35–55). Claim 13 is unpatentable under §103 as obvious over Wang.
Claim 14 depends from claim 3 and recites element-wise absolute value calculation using sequential read-out and multi-bit quantization.
Wang et al. teaches sequential read-out of multi-bit RRAM weights combined with DAC/ADC conversion to implement nonlinear activation and post-processing operations (e.g., see Wang, col. 12, ll. 10–40). Claim 14 is unpatentable under §103 as obvious over Wang.
Claim 15 depends from claim 14 and recites accumulating sums using an adder and register across multiple clock cycles.
Wang et al. discloses accumulating partial sums from crossbar outputs using digital adders and registers across multiple cycles (e.g., see Wang, col. 13, ll. 5–25). Claim 15 is unpatentable under §103 as obvious over Wang.
Claim 16 depends from claim 14 and recites pointwise convolution using multiple RCMs and backend summation.
Wang et al. teaches mapping convolutional operations into pointwise crossbar computations using multiple crossbar macros and aggregating results digitally (e.g., see Wang, col. 14, ll. 1–35). Claim 16 is unpatentable under §103 as obvious over Wang.
Claim 17 depends from claim 3 and recites a subtraction architecture using dual arrays and differential sensing.
Choi et al. discloses subtraction using dual-array configurations and differential sensing of column currents (e.g., see Choi, Fig. 7; col. 9, ll. 10–35).
Accordingly, claim 17 is unpatentable under §103 as obvious over Choi.
Citation of Relevant Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Applicants are directed to consider additional pertinent prior art included on the Notice of References Cited (PTOL 892) attached herewith.
Conclusion
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HIEN N. NGUYEN
Primary Examiner
Art Unit 2824
/HN/
January 9, 2026
/HIEN N NGUYEN/Primary Examiner, Art Unit 2824
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