Prosecution Insights
Last updated: April 19, 2026
Application No. 18/476,545

DUAL-SIDE BRIDGE CHIPS CONNECTING TWO SEMICONDUCTOR CHIPS WITH STACKED SEMICONDUCTOR DEVICES

Non-Final OA §112
Filed
Sep 28, 2023
Examiner
HALL, VICTORIA KATHLEEN
Art Unit
2897
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
International Business Machines Corporation
OA Round
1 (Non-Final)
84%
Grant Probability
Favorable
1-2
OA Rounds
2y 6m
To Grant
99%
With Interview

Examiner Intelligence

Grants 84% — above average
84%
Career Allow Rate
678 granted / 811 resolved
+15.6% vs TC avg
Strong +19% interview lift
Without
With
+19.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
35 currently pending
Career history
846
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
38.7%
-1.3% vs TC avg
§102
19.9%
-20.1% vs TC avg
§112
31.8%
-8.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 811 resolved cases

Office Action

§112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Election/Restrictions Applicant’s election without traverse of claims 1-13 in the reply filed on January 9, 2026 is acknowledged. Drawings The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “ each of the plurality of through-silicon vias connect to a portion of the frontside interconnect wiring by a micro-bump ” of claim 12 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Specification The disclosure is objected to because of the following informalities: Page 17, paragraph 57, line 5: Change 5A to 5B. Page 20, paragraph 63, line 1: Check the language “can be formed and”. The current phrasing appears to be missing a word. Page 20, paragraph 63, line 11: Change 5A to 5B. Page 21, paragraph 62, lines 9-10: Top device 6B is not in chiplet 10A. Page 21, paragraph 62, line 10: Check “top device 6B and 8B” – 8B is a bottom device. Page 21, line 13: Change “FIG. 1” to “FIG. 2”. The hybrid bond 24 is in Figure 2, but not in Figure 1. Page 25, paragraph 75, first line of the page: Add a space between “10B).” and “For”. Page 26, paragraph 82, line 6: Change “surround” to “surrounds”. Page 28, paragraph 85, line 3 of the page : Change 8B to 8A, if this is what applicants intended. Page 28, paragraph 85, line 9 of the page: Review the reference to “bottom device 8B”. It appears from the context of this paragraph, that “top device 6A” was intended. Page 38, paragraph 126, line 4: Change 2A to 82A and 2B to 82B. Compare with paragraph 123, lines 2-3. Appropriate correction is required. Claim Objections Claims 1-13 are objected to because of the following informalities: Claim 1, line 7: Add “at least” before “two chiplets ”. Compare with line 2. Claims 2-13 are objected to for depending from objected-to base claim 1. Claim 9, line 2: Add “of” after “sidewalls”. Claim 9, line 3: Change “connects” to “connecting”. Claim 9, line 5: Change “connects” to “connecting”. Claim 9, line 7: Change “surrounds” to “surrounding”. Claim 9, line 8: Add “material” after “underfill”. Compare with line 7. Claim 9, line 10: Change “surrounds” to “surrounding”. Claim 9, line 11: Is the second underfill associated with the backside interconnect wiring or the frontside interconnect wiring? Note that the first underfill material appears to be adjacent the backside interconnect wiring because the first underfill material is between the first bridge chip and the packaging substrate. Claim 9, line 12: Change “contacts” to “contacting”. Claim 9, line 13: Change “the two at least” to “the at least two”. Claims 11-13 are objected to for depending from objected-to base claim 9. Claim 10, line 2: Add “of” after “sidewalls”. Claim 10, line 3: Change “connects” to “connecting”. Claim 10, line 5: Change “connects” to “connecting”. Claim 10, line 8: Change “is” to “being”. Claim 10, line 11: Change “is” to “being”. Claim 10, line 13: Change “surrounds” to “surrounding”. Note : Although claims 14-20 are currently withdrawn, the Office is including the following objections to advance prosecution in the event that the claims are re-joined. Claim 19, line 4: It appears that the substrate in this line is the remnant of the second wafer of claim 14, lines 13-14. If so, before the period on line 5, “wherein the substrate is the portion of the second wafer with the plurality of through-silicon vias”. Claim 20: This language appears to involve the use of a mental process for selecting the top and bottom semiconductor devices. The Office suggests replacing the text of claim 20 with: “20. The method of claim 14, wherein the top semiconductor device is selected from the group consisting of a logic device and a memory device; and wherein the bottom semiconductor device is selected from the group consisting of the logic device and the memory device.” Appropriate correction is required. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b ) CONCLUSION.— The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the appl icant regards as his invention. Claims 1-13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Regarding claim 1: Claim 1 defines the at least two chiplets as follows: at least two chiplets , wherein each chiplet includes a top semiconductor device with frontside interconnect wiring contacting a substrate with a plurality of through-silicon vias, wherein the top semiconductor device contacts a bottom semiconductor device with backside interconnect wiring; …. However, this language suggests that the chiplet is defined to be the top semiconductor device with frontside interconnect wiring, with the substrate with the plurality of through-silicon vias and the bottom semiconductor device with backside interconnect wiring being separate. Because the language is confusing as to what the chiplet encompasses, claim 1 is rejected as indefinite. Claims 2-13 are rejected for depending from rejected base claim 1. Regarding claim 9, which depends from claim 1: This claim requires that “ a second underfill surrounds a plurality of micro-bumps and between the second bridge chip and a portion of the backside interconnect wiring ;… .” However, claim 9 does not indicate what the plurality of micro-bumps is associated with. Because this is unclear from the claim language, claim 9 is rejected as indefinite. Claims 11-13 are rejected for depending from rejected base claim 9. Regarding claim 10, which depends from claim 1: This claim requires that “ a third underfill material surrounds the plurality of micro-bumps connecting the second bridge chip to each of the substrate with the plurality of through-silicon vias. ” However, earlier in the claim, the claim defines the location of the plurality of micro-bumps as follows: “ a plurality of micro-bumps connects a first portion of the backside interconnect wiring of each chiplet of the at least two chiplets to the first bridge chip; … .” Thus, the plurality of micro-bumps is associated with the first bridge chip, not the second bridge chip. Because claim 10 defines the location of the plurality of micro-bumps and then places the plurality of micro-bumps is another location, claim 10 is rejected as indefinite. Regarding claim 13, which depends from claim 11, which depends from claim 9, which depends from claim 1: Claim 13 requires “ wherein the second bridge chip connects the frontside interconnect wiring in each chiplet of the at least two chiplets , further comprises the plurality of micro-bumps on each chiplet of the at least two chiplets connected to the plurality of through-silicon to the second bridge chip .” This language associates the plurality of micro-bumps as being on each chiplet , in other words, two pluralities of micro-bumps, one for each chiplet . However, claim 9, which defines the plurality of micro-bumps, recites that the second underfill surrounds a plurality of micro-bumps . Two pluralities of micro-bumps, one plurality associated with one chiplet , is not defined in claim 9. Because the language is confusing as to what the plurality (or pluralities) of micro-bumps are associated with, claim 13 is rejected as indefinite. Allowable Subject Matter Claims 1-13 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), 2nd paragraph, set forth in this Office action. The following is a statement of reasons for the indication of allowable subject matter: With regard to claim 1: The claim has been found allowable because the prior art of record does not disclose “ at least two chiplets , wherein each chiplet includes a top semiconductor device with frontside interconnect wiring contacting a substrate with a plurality of through-silicon vias, wherein the top semiconductor device contacts a bottom semiconductor device with backside interconnect wiring; a first bridge chip connects to a first portion of the backside interconnect wiring in each chiplet of the two chiplets ; and a second bridge chip connects the frontside interconnect wiring in each chiplet of the at least two chiplets ”, in combination with the remaining limitations of the claim. With regard to claims 2 -13 : The claims have been found allowable due to their dependency from claim 1 above. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT VICTORIA KATHLEEN HALL whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)270-7567 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT Monday-Friday, 8 a.m.-5 p.m. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT Fernando Toledo can be reached at FILLIN "SPE Phone?" \* MERGEFORMAT 571-272-1867 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Victoria K. Hall/ Primary Examiner, Art Unit 2897
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Prosecution Timeline

Sep 28, 2023
Application Filed
Mar 25, 2026
Non-Final Rejection — §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
84%
Grant Probability
99%
With Interview (+19.1%)
2y 6m
Median Time to Grant
Low
PTA Risk
Based on 811 resolved cases by this examiner. Grant probability derived from career allow rate.

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