Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
In response to the restriction requirement mailed on 11/24/2025, the Applicant elected Group II encompassing semiconductor device claims 16 and 17 with traverse on the basis that “…restriction is improper as a search can be made without serious burden, even if Group I and II are distinct or independent inventions.” The examiner respectfully disagrees.
On page 3 under line item number 2 of the restriction requirement, it was noted that “…there would be a serious search and examination burden if restriction were not requirement because…the inventions have acquired a separated status in the art in view of the different classification or that the inventions require a different field of search.
Further, a search for Groups I and II would not be coextensive, because a search indicating that the process of using is novel or unobvious would not extend to a holding that the product itself is novel or unobvious. Similarly, a search indicating that the product is known or would have been obvious would not extend to a holding that the process of using is known or would have been obvious.
Therefore, the restriction requirement is still deemed proper and is made FINAL.
Currently, claims 1-17 are pending, but non-elected Group II drawn to a method encompassing claims 1-15 has been withdrawn from the examination. Elected claims 16 and 17 are examined below.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement (IDS)
The information disclosure statement submitted on 09/28/2023 ("09-28-23 IDS") is in compliance with the provisions of 37 CFR 1.97. Accordingly, the 09-28-23 IDS is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: SEMICONDUCTOR DEVICE HAVING INTER-POLY OXIDE LAYER BETWEEN GATE POLYSILICON AND SHIELD POLYSILICON [[AND METHOD OF FORMING A SEMICONDUCTOR DEVICE]]
Claim Objections
Claim 17 is objected to because “the surface” lacks antecedent basis. Appropriate correction is required.
A. Prior-art rejection based on Hsieh
Claim Rejections - 35 USC § 1021
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 16 and 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pub. No. US 2022/0293786 A1 to Hsieh (“Hsieh”).
Fig. 3A of Hsieh has been annotated to support the rejections below:
[AltContent: textbox (S2)][AltContent: arrow][AltContent: textbox (S1)][AltContent: arrow][AltContent: textbox (234)]
PNG
media_image1.png
385
451
media_image1.png
Greyscale
Regarding independent claim 16, Hsieh teaches a semiconductor device (see Fig. 3A; see also Fig. 2C; para [0032] - “Please refer to FIG. 3A for another preferred embodiment of the present invention, the N-channel SGT MOSFET 300 has a similar structure to FIG. 2C, except that, each of the gate trenches further comprises dual gate trenches including a first type gate trench 301 and a second type gate trench 302 right below, wherein the first type gate trench 301 is filled with a gate electrode 303 and upper portion of a shielded gate electrode, the second type gate trench 302 is filled with lower portion of the shielded gate electrode 304.”), further comprising:
a substrate 234 comprising:
trenches 302;
an isolation oxide layer 306, 305, 307 (para [0032] - “…wherein the gate oxide 307 has thickness less than the first insulating film 305, the second insulating film 306 and the IPO film 308.”) in the trenches 302;
a shield polysilicon 304 in the trenches 302 and partially surrounded by the isolation oxide layer 306, 305, 307;
an inter-poly oxide (IPO) layer 308 on an upper surface of the shield polysilicon 304 and laterally surrounded by the isolation oxide layer 306, 305, 307;
a gate oxide layer 307 (of the isolation oxide layer 306, 305, 307) lining at least upper sidewalls of the trenches 302; and
a gate polysilicon 303 (para [0045] - “Another doped polysilicon is deposited and then etched back by CMP to fill upper portion of the first type gate trenches 301 to serve as gate electrodes 303.”) disposed on an upper surface of the IPO layer 308 and on an upper surface S1 of the isolation oxide layer 306, 305, 307 and laterally surrounded in the trenches 302 by the gate oxide layer 307 (of the isolation oxide layer 306, 305, 307);
wherein the contact surface of the gate polysilicon 303 with the IPO layer 308 and the isolation oxide layer 305, 306, 307 is substantially flat, and
wherein the isolation oxide layer 305, 306, 307 has a thickness that tapers from a greater thickness near the shield polysilicon 304 to a smaller thickness near a top opening of the trench 302.
Regarding claim 17, Hsieh teaches the thickness of the isolation oxide layer 305, 306, 307 tapers from the greater thickness near the shield polysilicon 304 to the smaller thickness near a top opening of the trench 302 so that the surface S2 of the isolation oxide layer 305, 306, 307 facing towards the center of the trench 302 has a convex shape.
B. Prior-art rejection based on Yilmaz
Claim Rejections - 35 USC § 102
Claims 16 and 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pub. No. US 2022/0393011 A1 to Shin (“Shin”).
Fig. 2A of Shin has been annotated to support the rejections below:
[AltContent: textbox (S1)][AltContent: arrow][AltContent: arrow][AltContent: textbox (S2)][AltContent: arrow]
PNG
media_image2.png
478
543
media_image2.png
Greyscale
Regarding independent claim 16, Shin teaches a semiconductor device (see Fig. 2A; see also Fig. 2B), further comprising:
a substrate 120 comprising:
trenches 130, 130 (para [0063] - “a gate trench 130”);
an isolation oxide layer 410, 440 (para [0064] - “A sidewall insulating layer 410”; para [0065] - “gate insulating layer 440”) in the trenches 130, 130;
a shield polysilicon 140 (para [0064] - In one or more examples, the source electrode 140 may be referred to as…a shield electrode...”) in the trenches 130, 130 and partially surrounded by the isolation oxide layer 410, 440;
an inter-poly oxide (IPO) layer 430 (para [0065] - “a first inter-electrode insulating layer 430”) on an upper surface of the shield polysilicon 140 and laterally surrounded by the isolation oxide layer 410, 440;
a gate oxide layer 440 (of the isolation oxide layer 410, 440) lining at least upper sidewalls of the trenches 130, 130; and
a gate polysilicon 145 (para [0065] - “Floating poly-Si (or floating gate poly) 145”) disposed on an upper surface of the IPO layer 430 and on an upper surface S1 of the isolation oxide layer 410, 440 and laterally surrounded in the trenches 130, 130 by the gate oxide layer 440;
wherein the contact surface of the gate polysilicon 145 with the IPO layer 430 and the isolation oxide layer 410, 440 is substantially flat, and
wherein the isolation oxide layer 410, 440 has a thickness that tapers from a greater thickness near the shield polysilicon 140 to a smaller thickness near a top opening of the trench 130, 130.
Regarding claim 17, Shin teaches the thickness of the isolation oxide layer 410, 440 tapers from the greater thickness near the shield polysilicon 140 to the smaller thickness near a top opening of the trench 130, 130 so that the surface S2 of the isolation oxide layer 410, 440 facing towards the center of the trench 130, 130 has a convex shape.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Pub. No. US 2022/0037523 A1 to Oda et al.
Pub. No. US 2021/0126124 A1 to Hsieh
Pub. No. US 2020/0111896 A1 to Feil et al.
Pub. No. US 2010/0244126 A1 to Purtell et al.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL JUNG whose telephone number is (408) 918-7554. The examiner can normally be reached on 8:30 A.M. to 7 P.M.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached on (571) 272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MICHAEL JUNG/Primary Examiner, Art Unit 2817 06 February 2026
1 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status