Prosecution Insights
Last updated: August 18, 2026
Application No. 18/476,773

DOHERTY AMPLIFIER CIRCUIT

Non-Final OA §102§112
Filed
Sep 28, 2023
Priority
Sep 29, 2022 — JP 2022-156825
Examiner
NGUYEN, KHIEM D
Art Unit
2843
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Murata Manufacturing Co., Ltd.
OA Round
2 (Non-Final)
86%
Grant Probability
Favorable
2-3
OA Rounds
0m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allowance Rate
1916 granted / 2234 resolved
+17.8% vs TC avg
Moderate +12% lift
Without
With
+12.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
53 currently pending
Career history
2276
Total Applications
across all art units

Statute-Specific Performance

§101
0.8%
-39.2% vs TC avg
§103
46.3%
+6.3% vs TC avg
§102
29.0%
-11.0% vs TC avg
§112
15.9%
-24.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 2234 resolved cases

Office Action

§102 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement The information disclosure statement (IDS) submitted on 06/11/2026. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Response to Arguments Applicant’s arguments with respect to claim(s) 1 & 3-11 have been considered but are moot because new found references, US 10050588 B2 and US 7218175 B1. Drawings The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “a feedback circuit configured to provide a voltage or a current based on the amplified radio frequency signal to an emitter or a source of the transistor, wherein the feedback circuit comprises a resistor that is electrically coupled between the emitter or the source of the transistor and a reference potential” in Claim 6 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 6 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. In Claim 6, lines 11-12, the recitation of “the feedback circuit comprises a resistor that is electrically coupled between the emitter or the source of the transistor and a reference potential” is not clear because the feedback circuit configured to provide a voltage or a current based on the amplified radio frequency signal to the base of the transistor. It is noted that the feedback circuit that includes resistor being connected between collector and base of transistor Q as shown in Fig. 2 of the application. It is not clear as to how the feedback circuit would to provide a voltage or a current based on the amplified radio frequency signal to an emitter or a source of the transistor, wherein the feedback circuit comprises a resistor that is electrically coupled between the emitter or the source of the transistor and a reference potential. Further clarification. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1, 3 & 6-11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by de Jong et . (US 10,050,588 B2), hereinafter, de Jong. Regarding claim 1: de Jong discloses in Figs. 1-2, 7-8, a Doherty amplifier circuit comprising: a carrier amplifier (Fig. 2: circuit 212) comprising one or more first amplifiers (amplifiers 212a, 212b, 21c); and a peaking amplifier (Fig. 2: circuit 214) comprising one or more second amplifiers (amplifiers 214a, 214b, 214c), wherein at least one amplifier of the first amplifiers or the second amplifiers comprises: a transistor (Fig. 7: transistor 766) that receives a radio frequency signal (input signal “in”) and that receives a changing bias voltage or a changing bias current at a base (base of transistor 766) or a gate of the transistor, and that outputs an amplified radio frequency signal from a collector (collector of transistor 766) or a drain of the transistor, and a feedback circuit (Fig. 7: circuit includes resistor R2 and capacitor C2) configured to provide a voltage or a current based on the amplified radio frequency signal to the base or the gate of the transistor, or to an emitter or a source of the transistor, and wherein the feedback circuit comprises a resistor (resistor R2 or 765) electrically coupled between the base (base of transistor 766) or the gate of the transistor and the collector (collector of transistor 766) or the drain of the transistor. Regarding claim 3: de Jong discloses in Figs. 1-2, 7-8, the Doherty amplifier circuit according to Claim 1, wherein the feedback circuit further comprises a capacitor (capacitor C2) coupled in series to the resistor (resistor R2 as shown in Fig. 7). Regarding claim 6 as best understood, Claim 6 is rejected in the same manner as discussed above in Claim 1. Regarding claim 7: de Jong discloses in Figs. 1-2, 7-8, the Doherty amplifier circuit according to Claim 1, wherein the bias voltage or the bias current changes based on an envelope of a radio frequency signal (Figs. 102, input signal) amplified by the Doherty amplifier circuit. Regarding claim 8: de Jong discloses in Figs. 1-2, 7-8, the Doherty amplifier circuit according to Claim 1, wherein the bias voltage or the bias current changes based on a power supply voltage (supply Vsup, V2, of Fig. 7) of the Doherty amplifier circuit. Regarding claim 9: de Jong discloses in Figs. 1-2, 7-8, the Doherty amplifier circuit according to Claim 1, wherein the bias voltage or the bias current changes based on a temperature of the Doherty amplifier circuit (Col 2, lines 7-15, temperature, In one or more embodiments the Doherty amplifier further comprises a controller that is configured to: receive one or more sensed-temperature-signals; and set control parameters of the variable splitter-attenuator and/or the variable splitter-phase-shifter based on the sensed-temperature-signals. In one or more embodiments the sensed-temperature-signals are representative of: a temperature of the integrated circuit, or a temperature of the main-power-amplifier or the peaking-power-amplifier). Regarding claim 10: de Jong discloses in Figs. 1-2, 7-8, the Doherty amplifier circuit according to Claim 1, wherein the bias voltage or the bias current changes based on a saturation state of the carrier amplifier (Col. 12, last paragraph, making the class C threshold in the peaking path programmable, since this determines the take-over point where the peaking amplifier starts helping the main amplifier to deliver power to the load. The class C threshold can be programmed based on the operating frequency, temperature, load impedance or supply voltage, for example. It can also be programmed based on the specific process spread that a product realization of the Doherty amplifier circuit has experienced. Hence, programming this peaking amplifier threshold can be part of the calibration or self-calibration of the Doherty amplifier circuit). Regarding claim 11: de Jong discloses in Figs. 1-2, 7-8, the Doherty amplifier circuit according to Claim 1, wherein the bias voltage or the bias current changes based on a reflection power of the Doherty amplifier circuit (Col. 13, lines 39-44, both the main- and peaking amplifier chain are equipped with multiple gain stages. This can yield a nearly signal-strength independent loading on the input power splitter and it can provide a large amount of power gain which is beneficial for the power-added efficiency and can be convenient for the end user). Claim 6 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by de Kobayashi (US 7,218,175 B1) Regarding claim 6 as best understood: Kobayashi discloses in Figs. 4-6, a Doherty amplifier circuit comprising: a carrier amplifier (Fig. 5: circuit 202) comprising one or more first amplifiers; and a peaking amplifier (204) comprising one or more second amplifiers, wherein at least one amplifier of the first amplifiers or the second amplifiers comprises: a transistor (Fig. 4: transistor Q1) that receives a radio frequency signal (input signal IN) and that receives a changing bias voltage or a changing bias current at a base (base of transistor Q1) or a gate of the transistor, and that outputs an amplified radio frequency signal from a collector (collector of Q1) or a drain of the transistor, and a feedback circuit (circuit includes resistor RFB and capacitor CFB) configured to provide a voltage or a current based on the amplified radio frequency signal to the base or the gate of the transistor (base of Q1) wherein a resistor (Fig. 4: resistor RFB) that is electrically coupled between the emitter or the source of the transistor and a reference potential (reference ground). Allowable Subject Matter Claims 4-5 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claims 4-5 are allowable since the closest prior art (i.e. de Jong) does not discloses wherein the at least one amplifier comprises a plurality of cells, each cell comprising a plurality of unit transistors of the transistor, and each cell comprising a plurality of unit resistors of the resistor, and wherein the capacitor is a common capacitor for the plurality of cells. Claim 5 is allowable because it depends on claim 4. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHIEM D NGUYEN whose telephone number is (571)270-3941. The examiner can normally be reached Mon-Fri 8:00 AM-5:00 PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Han can be reached at (571) 272-2078. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /KHIEM D NGUYEN/Examiner, Art Unit 2843
Read full office action

Prosecution Timeline

Sep 28, 2023
Application Filed
Jan 27, 2026
Non-Final Rejection mailed — §102, §112
Apr 27, 2026
Response Filed
Jul 23, 2026
Non-Final Rejection mailed — §102, §112 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

2-3
Expected OA Rounds
86%
Grant Probability
98%
With Interview (+12.5%)
2y 3m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 2234 resolved cases by this examiner. Grant probability derived from career allowance rate.

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