Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement filed September 28, 2023 fails to comply with 37 CFR 1.98(a)(2), which requires a legible copy of each cited foreign patent document; each non-patent literature publication or that portion which caused it to be listed; and all other information or that portion which caused it to be listed. Therefore, the non patent literature document under cite no. C4 titled “Rambus HBM subsystem more than doubles HBM2E speed” has not been considered as the copy provided is illegible.
Specification
The disclosure is objected to because of the following informalities:
Paragraph 4 reads “Over the past, various systems and methods have been proposed…” should likely read “In the past, various systems and methods have been proposed…” or similar.
Paragraph 34 has a typographical error, “magnetoresistive rand random-access memory (MRAM)” should likely read “magnetoresistive random-access memory (MRAM)”.
Paragraph 50 reads “Depending on the implementation, interposer 304 and substrate 302 can both be configured to establish connections across semiconductor 302.” Should likely read “Depending on the implementation, interposer 304 and substrate 302 can both be configured to establish connections across semiconductor device 300” or similar.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Keeth et al (Pub. No. US20190179769A1), hereinafter referred to as Keeth, in view of Song et al. (US Patent No. 10,475,774), hereinafter referred to as Song, and in further view of Rubin et al (Pub. No. US20230197705A1), hereinafter referred to as Rubin.
Regarding claim 1, Keeth teaches an apparatus comprising a first circuit comprising a first interface (Fig. 2, host device 105-a; ¶32); a second circuit coupled to the first circuit, the second circuit comprising a second interface and a third interface, the third interface being coupled to the first interface (Fig. 4, translation device 400, HD PHY 405, MD PHY 410, host device 105-c, channels 220-b; ¶43-44 & ¶53); an interposer coupled to the second circuit (Fig. 2, translation device 205, silicon interposer 210; ¶34); and a first memory device coupled to the interposer, the first memory device comprising a fourth interface (Fig. 2, memory device 110-a; ¶32), the fourth interface being coupled to the second interface (Fig. 4, MD PHY 410, memory device 110-c, channels 225-b; ¶45-46). However, Keeth does not teach the first memory device being coupled to the interposer. Keeth also does not teach the second interface being characterized by a first data rate, the third interface being characterized by a second data rate, and the second date rate being greater than the first data rate.
Song teaches a second interface being characterized by a first data rate (Fig. 1, first data transfer lines TL1, first data transfer rate DTR1; Col. 3, line 46 – Col. 4, line 6 & Col. 4, lines 18-27), a third interface being characterized by a second data rate (Fig. 1, second data transfer lines TL2, second data transfer rate DTR2; Col. 3, line 46 – Col. 4, line 6 & Col. 4, lines 18-27), and the second data rate is greater than the first data rate (Col. 4, lines 18-27).
Keeth and Song are analogous art as they are in the same field of endeavor of memory devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Keeth to incorporate the teachings of Song to have the second data rate associated with the third interface be greater than the first date rate associated with the second interface. For the purpose of improving the memory bandwidth without needing the memory chips to have faster speeds and without the need to increase the number of data transfer pins between the first and second circuits, as recognized by Song.
However, Keeth as modified by Song does not expressly teach the memory device being coupled to an interposer.
Rubin teaches the first memory device being coupled to the interposer (Fig. 4, HBMs 150, module substrates 105; ¶56-62).
Keeth, Song, and Rubin are all analogous art as they are in the same field of endeavor of memory devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Keeth in view of Song to incorporate the teachings of Rubin to have the memory device coupled to the interposer. For the purpose of ensuring high-fidelity data exchange between device components.
Regarding claim 2, Keeth further teaches a substrate coupled to the interposer (Fig. 2, silicon interposer 210, package substrate 215; ¶33).
Regarding claim 3, Keeth does not teach the first circuit being coupled to the substrate.
Rubin teaches the first circuit being coupled to the substrate (Fig. 5, central die 550, package substrate 405; ¶83-84).
Keeth and Rubin are analogous art as they are in the same field of endeavor of memory devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Keeth to incorporate the teachings of Rubin to have the first circuit coupled to the substrate. For the purpose of reducing the manufacturing costs by reducing the area of the interposer.
Regarding claim 4, Keeth further teaches the interposer comprising a first interconnect, and the first interface is coupled to the third interface through the first interconnect (Fig. 2, silicon interposer 210, channels 220; ¶33-34).
Regarding claim 5, Keeth further teaches the interposer comprising a second interconnect, and the second interface is coupled to the fourth interface through the second interconnect (Fig. 2, silicon interposer 210, channels 225 & 230; ¶35).
Regarding claim 6, Keeth further teaches the second circuit further comprising a controller configured to manage a data flow between the first memory device and the first circuit (Fig. 4, translation component 415; ¶47-51).
Regarding claim 7, Keeth further teaches the first memory device further comprising a high-bandwidth memory (¶27 & ¶30).
Regarding claim 8, Keeth does not teach a ratio of the second data rate to the first data rate being greater than 5:1.
Song teaches the ratio of the second data rate to the first data rate being greater than 5:1 (Col. 4, lines 18-27).
Keeth and Song are analogous art as they are in the same field of endeavor of memory devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Keeth to incorporate the teachings of Song to have the ratio of the second data rate to the first data rate being greater than 5:1. For the purpose of improving the memory bandwidth without needing the memory chips to have faster speeds and without the need to increase the number of data transfer pins between the first and second circuits, as recognized by Song.
Regarding claim 9, Keeth teaches an apparatus comprising a substrate; an interposer coupled to the substrate (Fig. 2, silicon interposer 210, package substrate 215; ¶33); a first circuit coupled to the interposer, the first circuit comprising a first interface (Fig. 2, host device 105-a, silicon interposer 210; ¶32-33); a second circuit coupled to the interposer (Fig. 2, translation device 205, silicon interposer 210; ¶34), the second circuit comprising a second interface and a third interface, the third interface being coupled to the first interface (Fig. 4, HD PHY 405, MD PHY 410, channels 220-b; ¶34, ¶43-45); and a first memory device comprising a fourth interface, the fourth interface being coupled to the second interface (Fig. 4, memory device 110-c, channels 225-b, MD PHY 410; ¶43-46). However, Keeth does not teach the first memory device being coupled to the interposer. Keeth also does not teach the second interface being characterized by a first data rate, the third interface being characterized by a second data rate, and the second data rate being greater than the first data rate.
Song teaches a second interface being characterized by a first data rate (Fig. 1, first data transfer lines TL1, first data transfer rate DTR1; Col. 3, line 46 – Col. 4, line 6 & Col. 4, lines 18-27), a third interface being characterized by a second data rate (Fig. 1, second data transfer lines TL2, second data transfer rate DTR2; Col. 3, line 46 – Col. 4, line 6 & Col. 4, lines 18-27), and the second data rate is greater than the first data rate (Col. 4, lines 18-27).
Keeth and Song are analogous art as they are in the same field of endeavor of memory devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Keeth to incorporate the teachings of Song to have the second data rate associated with the third interface be greater than the first date rate associated with the second interface. For the purpose of improving the memory bandwidth without needing the memory chips to have faster speeds and without the need to increase the number of data transfer pins between the first and second circuits, as recognized by Song.
However, Keeth as modified by Song does not expressly teach the memory device being coupled to an interposer.
Rubin teaches the first memory device being coupled to the interposer (Fig. 4, HBMs 150, module substrates 105; ¶56-62).
Keeth, Song, and Rubin are all analogous art as they are in the same field of endeavor of memory devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Keeth in view of Song to incorporate the teachings of Rubin to have the memory device coupled to the interposer. For the purpose of ensuring high-fidelity data exchange between device components.
Regarding claim 10, Keeth further teaches the interposer comprising a first interconnect, and the first interface is coupled to the third interface through the first interconnect (Fig. 2, silicon interposer 210, channels 220; ¶33-34).
Regarding claim 11, Keeth further teaches the interposer comprising a second interconnect, and the second interface is coupled to the fourth interface through the second interconnect (Fig. 2, silicon interposer 210, channels 225 & 230; ¶35).
Regarding claim 12, Keeth further teaches the second circuit further comprising a controller configured to manage a data flow between the first memory device and the first circuit (Fig. 4, translation component 415; ¶47-51).
Regarding claim 13, Keeth further teaches the first memory device further comprising a high-bandwidth memory (¶27 & ¶30).
Regarding claim 14, Keeth does not teach a ratio of the second data rate to the first data rate being greater than 5:1.
Song teaches the ratio of the second data rate to the first data rate being greater than 5:1 (Col. 4, lines 18-27).
Keeth and Song are analogous art as they are in the same field of endeavor of memory devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Keeth to incorporate the teachings of Song to have the ratio of the second data rate to the first data rate being greater than 5:1. For the purpose of improving the memory bandwidth without needing the memory chips to have faster speeds and without the need to increase the number of data transfer pins between the first and second circuits, as recognized by Song.
Regarding claim 15, Keeth teaches an apparatus comprising a substrate (Fig. 2, package substrate 215; ¶33); a first circuit first circuit comprising a first interface (Fig. 2, host device 105-a; ¶32); a second circuit coupled to the first circuit, the second circuit comprising a second interface and a third interface, the third interface being coupled to the first interface (Fig. 4, translation device 400, HD PHY 405, MD PHY 410, host device 105-c, channels 220-b; ¶43-44 & ¶53); and a first memory device coupled to the second circuit, the first memory device comprising a fourth interface, the fourth interface being coupled to the second interface (Fig. 4, memory device 110-c, channels 225-b, MD PHY 410; ¶43-46). However, Keeth does not teach the first circuit being coupled to the substrate. Keeth also does not teach the second interface being characterized by a first data rate, the third interface being characterized by a second data rate, and the second data rate being greater than the first data rate.
Song teaches a second interface being characterized by a first data rate (Fig. 1, first data transfer lines TL1, first data transfer rate DTR1; Col. 3, line 46 – Col. 4, line 6 & Col. 4, lines 18-27), a third interface being characterized by a second data rate (Fig. 1, second data transfer lines TL2, second data transfer rate DTR2; Col. 3, line 46 – Col. 4, line 6 & Col. 4, lines 18-27), and the second data rate is greater than the first data rate (Col. 4, lines 18-27).
Keeth and Song are analogous art as they are in the same field of endeavor of memory devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Keeth to incorporate the teachings of Song to have the second data rate associated with the third interface be greater than the first date rate associated with the second interface. For the purpose of improving the memory bandwidth without needing the memory chips to have faster speeds and without the need to increase the number of data transfer pins between the first and second circuits, as recognized by Song.
However, Keeth as modified by Song does not expressly teach the first circuit being coupled to the substrate.
Rubin teaches the first circuit being coupled to the substrate (Fig. 5, central die 550, package substrate 405; ¶83-84).
Keeth, Song, and Rubin are all analogous art as they are in the same field of endeavor of memory devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Keeth in view of Song to incorporate the teachings of Rubin to have the first circuit coupled to the substrate. For the purpose of reducing the manufacturing costs by reducing the area of the interposer.
Regarding claim 16, Keeth further teaches an interposer coupled between the substrate and the second circuit (Fig. 2, translation device 205, silicon interposer 210, package substrate 215; ¶33-34).
Regarding claim 17, Keeth does not teach a second memory device which is coupled to the second circuit.
Song teaches a second memory device (Fig. 1, memory chips 110; Col. 2, line 64 – Col. 3, line 9), the second memory device coupled to the second circuit (Fig. 1, buffer chip 310, first data transfer line TL1; Col. 3, lines 29-32).
Keeth and Song are analogous art as they are in the same field of endeavor of memory devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Keeth to incorporate the teachings of Song to include a second memory device that is coupled to the second circuit. For the purpose of increasing memory bandwidth without having to develop faster chips, as recognized by Song.
Regarding claim 18, Keeth does not teach the second circuit further comprising a fifth interface, and the second memory device comprising a sixth interface coupled to the fifth interface.
Song teaches the second circuit further comprising a fifth interface (Fig. 1, data transfer pins 330a; Col. 3, line 46 – Col. 4, line 17), and the second memory device comprising a sixth interface coupled to the fifth interface (Fig. 1, data transfer pins 130; Col. 3, line 46 – Col. 4, line 17).
Keeth and Song are analogous art as they are in the same field of endeavor of memory devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Keeth to incorporate the teachings of Song to include a second memory device with a sixth interface and to have the second circuit further comprise a fifth interface where the sixth interface is coupled to the fifth interface. For the purpose of allowing device components to connect and interact with other components.
Regarding claim 19, Keeth further teaches the second circuit comprising a controller configured to manage a data flow between the first memory device and the first circuit (Fig. 4, translation component 415; ¶47-51).
Regarding claim 20, Keeth does not teach a ratio of the second data rate to the first data rate being greater than 5:1.
Song teaches the ratio of the second data rate to the first data rate being greater than 5:1 (Col. 4, lines 18-27).
Keeth and Song are analogous art as they are in the same field of endeavor of memory devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Keeth to incorporate the teachings of Song to have the ratio of the second data rate to the first data rate being greater than 5:1. For the purpose of improving the memory bandwidth without needing the memory chips to have faster speeds and without the need to increase the number of data transfer pins between the first and second circuits, as recognized by Song.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Camarota (Pub. No. US20180047663A1) and Dokania et al. (Pub. No. WO2020242781A1).
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/E.A.T./Examiner, Art Unit 2897