DETAILED ACTION
As per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
In responding to this Office action, the applicant is requested to include specific references (figures, paragraphs, lines, etc.) to the drawings/specification of the present application and/or the cited prior arts that clearly support any amendments/arguments presented in the response, to facilitate consideration of the amendments/arguments.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Should applicant desire to obtain the benefit of foreign priority under 35 U.S.C. 119(a)-(d) prior to declaration of an interference, a certified English translation of the foreign application must be submitted in reply to this action. 37 CFR 41.154(b) and 41.202(e). Failure to provide a certified translation may result in no benefit being accorded for the non-English application.
Amendment
Acknowledgment is made of applicant's Amendment, filed 02-26-2026. The changes and remarks disclosed therein have been considered.
Claim(s) 1, 5, 9, 13, and 15 has/have been amended, claim(s) 12 and 16 has/have been cancelled, and claim(s) 1-11, 13-15, 17-22, and 24 remain(s) pending in the application.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 1-11, 13-22, and 24 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim(s) 1, 5, 9, and 13 recite(s) the language (emphasis added) “during a normal operation such as a write or read operation”, where the language “such as” is exemplary claim language (see MPEP 2173.05(d)). Claim language must particularly point out and distinctly claim the subject matter and the use of exemplary language in claim renders the scope indefinite and thus not patentable.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 5-7, 9, 11, 13, and 15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee, US 20190279709 A1.
As to claim 1, Lee discloses a semiconductor device (see Lee Fig 4) comprising:
a voltage generation circuit (see Lee Fig 1B and Para [0030]) configured to generate a driving voltage (see Lee Fig 1B Ref VBL) in response to a voltage control signal (see Lee Fig 1B Ref VCLP); a row decoder (see Lee Fig 4 Ref 122) configured to select a word line (see Lee Fig 6 Ref WL19 and Para [0075]; Selecting a word line does not preclude other word lines from being selected.), among a plurality of word lines (see Lee Fig 6 Refs WL1-WL32), in response to a row address signal (see Lee Fig 4 Ref ADDR), and configured to apply the driving voltage to the selected word line (Voltages applied to either interconnect passes to the other during operations.); a column decoder (see Lee Fig 4 Ref 123) configured to select at least one bit line (see Lee Fig 6 Ref BL14), among a specific bit line (see Lee Fig 6 Ref RBL2 and Para [0054]) and a plurality of bit lines (see Lee Fig 6 Refs BL1-32), in response to a column address signal (see Lee Fig 4 Ref ADDR); and
a control circuit (see Lee Fig 4 Refs 120 and ADDR; The off chip signals come from a controller.) configured to generate the voltage control signal, the row address signal, and the column address signal, and configured to control the row decoder to select the word line and the column decoder (see Lee Fig 4 Refs 120; The disclosed circuit controls the decoders.) to select the specific bit line and at least one of the plurality of bit lines (see Lee Fig 6 Ref BL14) in a firing operation (see Lee Paras [0055], [0058], [0062], and [0068]), wherein
the driving voltage applied to the selected word line during the firing operation is higher than (see Lee Para [0055], Fig 3B Ref HRS, and Fig 10 Ref S1400; Out of range currents have lower voltages on specific word lines than normal operation voltages on selected word lines.) a driving voltage applied during a normal operation (see Lee Para [0058]) such as a write or read operation (see MPEP 2173.05(d)).
As to claim 2, Lee discloses the semiconductor device of claim 1, wherein
the control circuit generates the column address signal so that the column decoder selects one of the plurality of bit lines in a normal operation (see Lee Para [0058]).
As to claim 3, Lee discloses the semiconductor device of claim 2, further comprising
a cell array (see Lee Fig 4 Ref 110) comprising first memory cells (see Lee Fig 4 Ref 112) connected to the plurality of bit lines and second memory cells (see Lee Fig 4 Ref 114) connected to the specific bit line.
As to claim 5, Lee discloses a semiconductor device comprising:
a voltage generation circuit (see Lee Fig 1B and Para [0030]) configured to generate a driving voltage (see Lee Fig 1B Ref VBL) in response to a voltage control signal (see Lee Fig 1B Ref VCLP); a row decoder (see Lee Fig 4 Ref 122) configured to select at least one word line (see Lee Fig 6 Ref WL19 and Para [0075]), among a specific word line (see Lee Fig 6 Ref RWL27) and a plurality of word lines (see Lee Fig 6 Refs WL1-WL32), in response to a row address signal (see Lee Fig 4 Ref ADDR), and configured to apply the driving voltage to the at least one word line (Voltages applied to either interconnect passes to the other during operations.); a column decoder (see Lee Fig 4 Ref 123) configured to select at a bit line (see Lee Fig 6 Ref BL14; Selecting a bit line does not preclude other bit lines from being selected.), among the plurality of bit lines, in response to a column address signal (see Lee Fig 4 Ref ADDR); and a control circuit (see Lee Fig 4 Refs 120 and ADDR; The off chip signals come from a controller.) configured to generate the voltage control signal, the row address signal, and the column address signal, and configured to control the row decoder to select the specific word line and at least one of the plurality of word lines (see Lee Fig 6 Ref WL19) and the column decoder to select the bit line (see Lee Fig 4 Ref 120) in a firing operation (see Lee Paras [0055], [0058], [0062], and [0068]), wherein
the driving voltage applied to the at least one word line during the firing operation is higher than (see Lee Para [0055], Fig 3B Ref HRS, and Fig 10 Ref S1400; Out of range currents have lower voltages on specific word lines than normal operation voltages on selected word lines.) a driving voltage applied during a normal operation (see Lee Para [0058]) such as a write or read operation (see MPEP 2173.05(d)).
As to claim 6, Lee discloses the semiconductor device of claim 5, wherein
the control circuit generates the row address signal to select one of the plurality of word lines in a normal operation (see Lee Para [0058]).
As to claim 7, Lee discloses the semiconductor device of claim 6, further comprising
a cell array (see Lee Fig 4 Ref 110) comprising first memory cells (see Lee Fig 4 Ref 112) connected to the plurality of word lines and second memory cells (see Lee Fig 4 Ref 114) connected to the specific word line.
As to claim 9, Lee discloses an operating method of a semiconductor device (see Lee Fig 4), the method comprising:
performing a firing operation (see Lee Paras [0055], [0058], and [0068]) that comprises: selecting a specific bit line (see Lee Fig 6 Ref RBL2 and Para [0054]) and at least one of a plurality of bit lines (see Lee Fig 6 Ref BL14); selecting one of a plurality of word lines (see Lee Fig 6 Ref WL19 and Para [0075]); and applying a driving voltage to the selected word line (see Lee Fig 1B Ref VBL; Voltages applied to either interconnect passes to the other during operations.), wherein
the driving voltage applied to the selected word line during the firing operation is higher than (see Lee Para [0055], Fig 3B Ref HRS, and Fig 10 Ref S1400; Out of range currents have lower voltages on specific word lines than normal operation voltages on selected word lines.) a driving voltage applied during a normal operation (see Lee Para [0058]) such as a write or read operation (see MPEP 2173.05(d)).
As to claim 11, Lee discloses the operating method of claim 9, further comprising:
performing a normal operation that comprises: selecting one of the plurality of bit lines without selecting the specific bit line (see Lee Para [0058] and Fig 10; It is not necessary to simultaneously calibrate the reference current to select a memory cell.).
As to claim 13, Lee discloses an operating method of a semiconductor device (see Lee Fig 4), the method comprising:
performing a firing operation (see Lee Paras [0055], [0058], and [0068]) that comprises: selecting a specific word line (see Lee Fig 6 Ref RWL27) and one of a plurality of word lines (see Lee Fig 6 Refs WL1-WL32); selecting one of a plurality of bit lines (see Lee Fig 6 Refs BL1-32); and applying a driving voltage to the at least one selected word line (see Lee Fig 1B Ref VBL; Voltages applied to either interconnect passes to the other during operations.), wherein
the driving voltage applied to the selected specific word line and the selected one of the plurality of word lines during the firing operation is higher than (see Lee Para [0055], Fig 3B Ref HRS, and Fig 10 Ref S1400; Out of range currents have lower voltages on specific word lines than normal operation voltages on selected word lines.) a driving voltage applied during a normal operation (see Lee Para [0058]) such as a write or read operation (see MPEP 2173.05(d)).
As to claim 15, Lee discloses the operating method of claim 13, further comprising:
performing the normal operation that comprises: selecting at least one of the plurality of word lines without selecting the specific word line (see Lee Para [0058] and Fig 10; It is not necessary to simultaneously calibrate the reference current to select a memory cell.).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4, 8, 10, and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee, US 20190279709 A1.
As to claim 4, Lee discloses the semiconductor device of claim 3, wherein
threshold voltages of the second memory cells each have a relationship to threshold voltages of the first memory cells.
Lee does not appear to explicitly a lower voltage level than.
However, it would have been obvious to one skilled in the art at the time of the effective filing of the invention that a device, as disclosed by Lee, can be configured a particular transistors with high or low threshold voltages (see Lee Fig 3B and Fig 10). A higher or lower threshold relationship is a finite correspondence and it is obvious to try configure threshold relationship as one of the two.
As to claim 8, Lee discloses the semiconductor device of claim 7, wherein
threshold voltages of the second memory cells each have a lower voltage level than threshold voltages of the first memory cells (see Lee Fig 3B and Fig 10).
As to claim 10, Lee discloses the semiconductor device of claim 9, wherein
memory cells connected to the specific bit line each have a lower threshold voltage than memory cells connected to the plurality of bit lines (see Lee Fig 3B and Fig 10).
As to claim 14, Lee discloses the semiconductor device of claim 13, wherein
memory cells connected to the specific word line each have a lower threshold voltage than memory cells connected to the plurality of word lines (see Lee Fig 3B and Fig 10).
Claim(s) 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee, US 20190279709 A1, in view of Liaw, US 20060028889 A1.
As to claim 24, Lee discloses semiconductor device of claim 1, further comprising
a first memory cell (see Lee Fig 6 Refs RWL27 and RBL2) that is connected to the specific bit line (see Lee Fig 6 Ref RBL2) and a second memory cell (see Fig 6 Refs WL19 and BL14) that is connected between the selected word line (see Fig 6 Ref WL19) and one of the plurality of bit lines (see Fig 6 Refs BL14), wherein during the firing operation, current flows through the first and second memory cells (see Fig 1B Refs VSN and VREF and Para [0062]).
Lee does not appear to disclose a first memory cell that is connected between the selected word line and the specific bit line.
Liaw discloses a first memory cell (see Liaw Fig 3 Ref 318) that is connected between the selected word line (see Liaw Fig 3 Ref WL(=1)) and the specific bit line (see Liaw Fig 3 Ref BL_ref”1”).
It would have been obvious to one skilled in the art at the time of the effective filing of the invention that a semiconductor device, as disclosed by Lee, may have a particular interconnect arrangement, as disclosed by Liaw. The inventions are well known variants of memory devices which use reference array during sense operations, and the combination of known inventions which produces predictable results is obvious. Further evidence to the obviousness of their combination is their mutual attempt to improve the sensing margin (see Liaw Para [0005]).
Response to Arguments
Applicant's arguments filed 02/26/2026 have been fully considered but they are not persuasive.
The amended language does not appear to claim the invention with enough specificity to overcome the prior art, as the specific details of the firing operation are not explicitly recited in the claims and broadest reasonable interpretation has been applied.
Amending the claims with exemplary claim language does not overcome the prior rejection of record.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JEROME LARRY LEBOEUF whose telephone number is (571)272-7612. The examiner can normally be reached M-Th: 8:00AM - 6:00PM EST.
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/JEROME LEBOEUF/Primary Examiner, Art Unit 2824 - 04/10/2026
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