DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of invention Group I (claims 1-14) in the reply filed on 2/18/2026 is acknowledged.
Claims 15-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 2/18/2026.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 1 reciting “one or more substrate buildup layers positioned above the one or more thermal sources” and “one or more thermal vias formed in the one or more substrate buildup layers” renders the claim indefinite due to unclear correspondence. Firstly, it is unclear if the “one or more substrate buildup layers” are positioned above a same one of the one or more thermal sources or positioned above different ones of the one or more thermal sources. Furthermore, it is unclear if one or each of the one or more substrate buildup layers are positioned above each of “the one or more thermal sources” or positioned above one of “the one or more thermal sources”. For example, in case of plural substrate buildup layers and plural thermal sources, it is unclear which one of the following is the intended scope,
one of the substrate buildup layers is positioned on one of the thermal sources, or
one of the substrate buildup layers is positioned on each of the thermal sources, or
each of the plural substrate buildup layers is positioned on one of the thermal sources, or
each of the plural substrate buildup layers is positioned on a respective different ones of the thermal sources, or
each of the plural substrate buildup layers is positioned on each one of the thermal sources.
Similarly, it is unclear if the “one or more thermal vias” are formed in a same one of the one or substrate buildup layers or formed in different ones of the one or more thermal vias. Furthermore, it is also unclear if one or each of the one or more thermal vias are formed in each of “the one or more substrate buildup layers” or are formed in one of “the one or more substrate buildup layers”. For example, in case of plural thermal vias and plural substrate buildup layers, it is unclear which one of the following is the intended scope,
one of the thermal vias formed in one of the substrate buildup layers, or
one of the thermal vias formed in each of the substrate buildup layers, or
each of the plural thermal vias formed in one of the substrate buildup layers, or
each of the plural thermal vias formed in a respective different ones of the substrate buildup layers, or
each of the plural thermal vias formed in each one of the substrate buildup layers.
Claim 2 reciting “the one or more thermal vias land on the one or more thermal sources” renders the claim indefinite. Firstly, the intended scope of “land on” is unclear. Applicant’s disclosure does not describe thermal vias making physical contacts with the thermal source. Therefore, it is unclear what is required to constitute “land on”. Does it require some physical proximity or any thermal contact would constitutes “land on”?
The limitation is further indefinite due to unclear correspondence. For example, in case of plural thermal vias and plural thermal sources, it is unclear which one of the following is the intended scope,
one of the thermal vias lands on one of the thermal sources, or
one of the thermal vias lands on each of the thermal sources, or
each of the plural thermal vias lands on one of the thermal sources, or
each of the plural thermal vias lands on a respective different ones of the thermal sources, or
each of the plural thermal vias lands on each one of the thermal sources.
Claim 8 reciting “one or more substrate buildup layers positioned above the one or more thermal sources and having one or more thermal vias formed therein” renders the claim indefinite due to unclear correspondence for similar reasons as explained for claim 1 above.
Claim 9 reciting “the one or more thermal vias land on the one or more thermal sources” renders the claim indefinite due to unclear correspondence for similar reasons as explained for claim 2 above.
Other claims are rejected for depending on a rejected claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kang et al. US 2021/0118765 A1 (Kang).
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In re claim 1, as best understood, Kang discloses (e.g. FIG. 1) a semiconductor package substrate 110+140, comprising:
one or more thermal sources 121,122 (¶ 32-33) embedded in the semiconductor package substrate;
“one or more substrate buildup layers 141 positioned above the one or more thermal sources 122”; and
“one or more thermal vias 143HV formed in the one or more substrate buildup layers 141”.
In re claim 2, as best understood, Kang discloses (e.g. FIG. 1) wherein “the one or more thermal vias 143HV land on the one or more thermal sources 122”.
In re claim 3, Kang discloses (e.g. FIG. 1) wherein the one or more thermal vias 143HV include a plurality of stacked thermal vias (FIG. 1 shows six vertical stacks of thermal vias 143HV above die 122).
In re claim 4, Kang discloses (e.g. FIG. 1) wherein the one or more thermal vias 143HV include two or more pluralities of stacked vias that are offset from one another (six stacks above die 122 shown in FIG. 1, each being laterally offset from each other).
In re claim 5, Kang discloses (e.g. FIG. 1) wherein the one or more substrate buildup layers 141 include a plurality of substrate buildup layers 141 having one or more perforated copper layers 142 positioned therebetween (¶ 42, Cu wiring layers 142 being patterned and are therefore considered “perforated”).
In re claim 6, no specific “integrated voltage regulator” claimed that would distinguish over Kang teaching the one or more thermal sources 121,122 include an integrated voltage regulator (e.g. power management integrated circuit PMIC, ¶ 32).
In re claim 7, Kang teaches wherein the one or more thermal sources 121,122 include a capacitor (e.g. capacitors included in DRAM, ¶ 33).
In re claim 8, as best understood, Kang discloses (e.g. FIG. 1) a semiconductor package 100A, comprising:
a semiconductor device 125 (¶ 34);
a heat spreader 127+170 (¶ 52) positioned above the semiconductor device 125; and
a substrate 110+140 positioned below the semiconductor device 125, wherein the substrate 110+140 includes one or more thermal sources 121,122 (¶ 32-33) embedded therein and one or more substrate buildup layers 141 positioned above the one or more thermal sources 121,122 and having one or more thermal vias 143HV formed therein.
In re claim 9, as best understood, Kang discloses (e.g. FIG. 1) wherein “the one or more thermal vias 143HV land on the one or more thermal sources 122”.
In re claim 10, Kang discloses (e.g. FIG. 1) wherein the one or more thermal vias 143HV include a plurality of stacked thermal vias (FIG. 1 shows six vertical stacks of thermal vias 143HV above die 122).
In re claim 11, Kang discloses (e.g. FIG. 1) wherein the one or more thermal vias 143HV include two or more pluralities of stacked vias that are offset from one another (six stacks above die 122 shown in FIG. 1, each being laterally offset from each other).
In re claim 12, Kang discloses (e.g. FIG. 1) wherein the one or more substrate buildup layers 141 include a plurality of substrate buildup layers 141 having one or more perforated copper layers 142 positioned therebetween (¶ 42, Cu wiring layers 142 being patterned and are therefore considered “perforated”).
In re claim 13, no specific “integrated voltage regulator” claimed that would distinguish over Kang teaching the one or more thermal sources 121,122 include an integrated voltage regulator (e.g. power management integrated circuit PMIC, ¶ 32).
In re claim 14, Kang teaches wherein the one or more thermal sources 121,122 include a capacitor (e.g. capacitors included in DRAM, ¶ 33).
Claims 1-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Waidhas et al. US 2022/0415815 A1 (Waidhas).
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In re claim 1, as best understood, Waidhas discloses (e.g. FIG. 1) a semiconductor package substrate 148+150+133, comprising:
one or more thermal sources 102,103,105 (¶ 42) embedded in the semiconductor package substrate;
“one or more substrate buildup layers (insulating layers of 148, ¶ 36) positioned above the one or more thermal sources” 102,103,105; and
“one or more thermal vias (vias in 148 being formed of conductive material and are inherently thermally conductive, ¶ 36) formed in the one or more substrate buildup layers”.
In re claim 2, as best understood, Waidhas discloses (e.g. FIG. 1) wherein “the one or more thermal vias (vias in 148) land on the one or more thermal sources 102,103,105”.
In re claim 3, Waidhas discloses (e.g. FIG. 1) wherein the one or more thermal vias include a plurality of stacked thermal vias (plural vertical stacks of vias in 148).
In re claim 4, Waidhas discloses (e.g. FIG. 1) wherein the one or more thermal vias include two or more pluralities of stacked vias that are offset from one another (plural stacks of vias in 148 that are laterally offset, e.g. a stack of vias above leftmost die 103 is offset from a stack of vias above leftmost die 102).
In re claim 5, Waidhas discloses (e.g. FIG. 1) wherein the one or more substrate buildup layers include a plurality of substrate buildup layers (insulating layers in 148, ¶ 36) having one or more perforated copper layers positioned therebetween (copper conductive traces in 148 are patterned traces and are therefore considered “perforated”, ¶ 36).
In re claim 6, Waidhas discloses (e.g. FIG. 1) wherein the one or more thermal sources 103,105 include an integrated voltage regulator (no specific “integrated voltage regulator” claimed that would distinguish over Waidhas teaching second and third semiconductor dies 103,105 integrated with voltage regulars, ¶ 32,161,266).
In re claim 7, Waidhas discloses (e.g. FIG. 1) wherein the one or more thermal sources 102,103,105 include a capacitor (¶ 22,32,33).
In re claim 8, as best understood, Waidhas discloses (e.g. FIG. 1) a semiconductor package 100, comprising:
a semiconductor device 101;
a heat spreader 135 (¶ 42) positioned above the semiconductor device 101; and
a substrate 148+150+133 positioned below the semiconductor device 101, wherein the substrate includes one or more thermal sources 102,103,105 (¶ 42) embedded therein and one or more substrate buildup layers (insulating layers of 148, ¶ 36) positioned above the one or more thermal sources 102,103,105 and having one or more thermal vias formed therein (vias in 148 being formed of conductive material and are inherently thermally conductive, ¶ 36).
In re claim 9, as best understood, Waidhas discloses (e.g. FIG. 1) wherein “the one or more thermal vias (vias in 148) land on the one or more thermal sources 102,103,105”.
In re claim 10, Waidhas discloses (e.g. FIG. 1) wherein the one or more thermal vias include a plurality of stacked thermal vias (plural vertical stacks of vias in 148).
In re claim 11, Waidhas discloses (e.g. FIG. 1) wherein the one or more thermal vias include two or more pluralities of stacked vias that are offset from one another (plural stacks of vias in 148 that are laterally offset, e.g. a stack of vias above leftmost die 103 is offset from a stack of vias above leftmost die 102).
In re claim 12, Waidhas discloses (e.g. FIG. 1) wherein the one or more substrate buildup layers include a plurality of substrate buildup layers (insulating layers in 148, ¶ 36) having one or more perforated copper layers positioned therebetween (copper conductive traces in 148 are patterned traces and are therefore considered “perforated”, ¶ 36).
In re claim 13, Waidhas discloses (e.g. FIG. 1) wherein the one or more thermal sources 103,105 include an integrated voltage regulator (no specific “integrated voltage regulator” claimed that would distinguish over Waidhas teaching second and third semiconductor dies 103,105 integrated with voltage regulars, ¶ 32,161,266).
In re claim 14, Waidhas discloses (e.g. FIG. 1) wherein the one or more thermal sources 102,103,105 include a capacitor (¶ 22,32,33).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YU CHEN whose telephone number is (571)270-7881. The examiner can normally be reached Monday-Friday: 9AM-5PM ET.
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/YU CHEN/Primary Examiner, Art Unit 2896
YU CHEN
Examiner
Art Unit 2896
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