DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-7, 14, 17, and 18 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Denda (JP 2016096188A).
In reference to claim 1, Denda (JP 2016096188A), a machine translation of which is included herewith and cited herein, discloses a semiconductor module, comprising:
a laminated substrate, 2 in Figure 1, configured by laminating an insulating plate 3 having an upper surface and a lower surface opposite to each other in an up-down direction, a heat dissipation plate 5 disposed on the lower surface of the insulating plate, and a circuit plate 4 disposed on the upper surface of the insulating plate, paragraph 14;
a semiconductor element 6 disposed on an upper surface of the circuit plate, paragraph 13;
a case 9 that surrounds the laminated substrate and has a space housing the semiconductor element;
a sealing resin 13 that fills the space of the case to seal the semiconductor element, paragraph 17; and
a partition wall 9a that extends in the up-down direction to divide the space filled with the sealing resin into a plurality of subspaces, the partition wall having a lower end and an upper end opposite to each other in the up-down direction, paragraph 25, wherein
at least a portion of the lower end of the partition wall is connected to the upper surface of the circuit plate, Figure 1 and paragraph 30.
In reference to claim 2, Denda discloses the insulating plate and/or the heat dissipation plate includes a plurality of curved portions protruding downward away from the semiconductor element, and each of the plurality of curved portions is located at a position immediately below a corresponding one of the plurality of subspaces, paragraphs 20 and 28
In reference to claim 3, Denda discloses a boundary between an adjacent two of the plurality of curved portions is located at a position immediately below the partition wall, paragraph 28.
In reference to claim 4, Denda discloses each of the plurality of subspaces is filled with the sealing resin, 13 in figure 1, and has a curved upper surface that is recessed downward toward the semiconductor element, paragraph 6.
In reference to claim 5, Denda discloses the partition wall is located at a boundary between an adjacent two of the plurality of subspaces, paragraphs 25 and 26.
In reference to claim 6, Denda discloses the case 9 includes first and second side walls that face each other, the semiconductor element 6 being disposed between the first and second walls, the partition wall 9a includes: a first beam connected to the first side wall; a second beam connected to the second side wall; and a wall portion connecting the first beam to the second beam and extending in the up-down direction to divide the space into at least two of the plurality of subspaces, and the wall portion has a lower end and an upper end opposite to each other in the up-down direction and at least a portion of the lower end of the wall portion is in contact with the upper surface of the circuit plate, Figure 2 and paragraphs 25, 27, and 30.
In reference to claim 7, Denda discloses a plurality of terminals 11 provided in each of the first and second side walls, paragraph 17.
In reference to claim 14, Denda discloses the partition wall has a cross shape when viewed from the up-down direction, 9a and 9b in Figure 2(a).
In reference to claim 17, Denda discloses the partition wall is made of a material identical to or at least partially identical to a material of the case, paragraph 27.
In reference to claim 18, Denda discloses a heat sink (cooling plate (not shown)) disposed on a lower surface of the heat dissipation plate 5 of the semiconductor module, paragraph 16.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 12, 13, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Denda (JP 2016096188A) in view of Bolognia (US 2017/0330812).
In reference to claim 12, Denda discloses the insulating plate has a rectangular shape elongated in a longitudinal direction (horizontal direction in Figure 2) and the first and second side walls face each other in a lateral direction orthogonal to the longitudinal direction.
Denda does not disclose the circuit plate is provided in plurality and the plurality of circuit plates are arranged side by side in the longitudinal direction on the insulating plate.
Bolognia (US 2017/0330812), hereafter “Bolognia,” discloses a semiconductor device package including teaching the insulating plate, 40 in Figure 5, has a rectangular shape elongated in a longitudinal direction, the circuit plate, “die attach pad (not shown)” corresponding to respective dies 26, paragraph 33, is provided in plurality and the plurality of circuit plates are arranged side by side in the longitudinal direction on the insulating plate, and the first and second side walls face each other in a lateral direction orthogonal to the longitudinal direction.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the circuit plate to be provided in plurality and the plurality of circuit plates to be arranged side by side in the longitudinal direction on the insulating plate. One would have been motivated to do so in order to package multiple dies in respective cavities that are not electrically coupled, paragraph 36.
In reference to claim 13, Bolognia discloses the partition wall includes a portion extending obliquely with respect to the longitudinal direction when viewed from the up-down direction, see Figure 6B annotated below.
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[AltContent: arrow][AltContent: arrow][AltContent: textbox (Oblique portions of partition wall )][AltContent: arrow][AltContent: arrow]
In reference to claim 16, Denda does not disclose the partition wall has a crank shape when viewed from the up-down direction.
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[AltContent: textbox (Crank shaped portion of the partition wall )][AltContent: arrow]Bolognia discloses a semiconductor package including teaching a partition wall has a crank shape when viewed from the up-down direction, see annotated Figure 6B below.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the partition wall has a crank shape when viewed from the up-down direction. To do so would have merely been a simple substitution of one known element for another to obtain predictable results; KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385, (2007), MPEP 2143 I. B. In this case substituting one partition wall shape for another to form cavities of different sizes and shapes, as suggested by Bolognia, paragraph 43.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Denda (JP 2016096188A) in view of Hung et al. (US 11,721,602).
In reference to claim 15, Denda does not disclose the partition wall has a T-shape when viewed from a direction orthogonal to the up-down direction.
Hung et al. (US 11,721,602) discloses a semiconductor device package including teaching a partition wall, 112a1 in Figure 2A, has a T-shape when viewed from a direction orthogonal to the up-down direction, col. 4, lines 7-22. It would have been obvious to one of ordinary skill in the art before the effective filing date of the inventio for the partition wall to have a T-shape when viewed from a direction orthogonal to the up-down direction. To do so would have merely been a simple substitution of one known element for another to obtain predictable results; KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385, (2007), MPEP 2143 I. B. In this case substituting one cross sectional shape of the partition wall for another.
Allowable Subject Matter
Claims 8-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 8 would be allowable because the prior art of record fails to teach or fairly suggest the structure wherein each of the first and second side walls has a stepped portion formed on an inner surface thereof, each of the plurality of terminals is embedded in a corresponding one of the first and second side walls, and an upper surface of each of the terminals is exposed from the corresponding one of the first and second side walls at the stepped portion, and a lower end of the first beam is in contact with the upper surface of a corresponding one of the plurality of terminals embedded in the first side wall; in combination with the other recited limitations in the respective claims and their base claims.
Claim 9 would be allowable because the prior art of record fails to teach or fairly suggest the structure wherein each of the first and second side walls has a stepped portion formed on an inner surface thereof, each of the plurality of terminals is embedded in a corresponding one of the first and second side walls, and an upper surface of each of the terminals is exposed from the corresponding one of the first and second side walls at the stepped portion, and the sealing resin is interposed between the second beam and the upper surface of a corresponding one of the plurality of terminals embedded in the second side wall; in combination with the other recited limitations in the respective claims and their base claims.
Claims 10 and 11 depend on claim 9 and would allowable in combination with the other recited limitations in the respective base claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Braden et al. (US 8,148,808), Chen et al. (US 2021/0305227), Chiu et al. (US 2020/0105640), Fritz et al. (US 2017/0127523), Nishimura (US 2022/0108959), and Pollack (US 6,534,711) disclose related semiconductor device housings sub-divided by partition walls.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRYAN R. JUNGE whose telephone number is (571)270-5717. The examiner can normally be reached M-F 8:00-4:30 CT.
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/BRYAN R JUNGE/ Primary Examiner, Art Unit 2897