DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 15-18 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 01/14/2026.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-14 and 19-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sukekawa et al. (U.S. 2021/0005611 A1; hereinafter Sukekawa).
With respect to claim 1, Sukekawa discloses a method comprising: providing a semiconductor substrate [14]; and forming isolating regions [85/43] (see ¶[0043] and ¶[0055]) between a plurality of adjacent vertical transistors [132] in the semiconductor substrate (See Figure 6B), wherein each vertical transistor of the plurality of adjacent vertical transistors extends along a vertical direction, and wherein two adjacent vertical transistors and a corresponding isolating region between the two adjacent vertical transistors are positioned along a horizontal direction perpendicular to the vertical direction (see Figure 6B), and wherein the corresponding isolating region comprises a conductive material (see ¶[0083]), and wherein, along the vertical direction, a length of the conductive material in the corresponding isolating region is greater than a length of a vertical gate [54] of each of the two adjacent vertical transistors (See Figure 6B and 14B).
With respect to claim 2, Sukekawa discloses wherein forming the isolating regions between the plurality of adjacent vertical transistors in the semiconductor substrate comprises: forming a plurality of trenches [116] in the semiconductor substrate, the plurality of trenches being positioned along the horizontal direction, each of the plurality of trenches extending along the vertical direction; and forming the corresponding isolating region by depositing the conductive material in a middle trench between two adjacent trenches for forming the two adjacent vertical transistors (See Figure 12A-B).
With respect to claim 3, Sukekawa discloses forming the two adjacent vertical transistors by depositing an isolating material [52] in the two adjacent trenches and then depositing at least one conductive layer [54] on the deposited isolating material in the two adjacent trenches to form the vertical gates of the two adjacent vertical transistors, wherein, along the vertical direction, a length of the deposited at least one conductive layer in each of the two adjacent trenches is smaller than the length of the conductive material filled in the middle trench (see ¶[0075] and Figures 12A-B).
With respect to claim 4, Sukekawa discloses wherein the semiconductor substrate comprises a first side and a second side opposite to the first side, wherein forming the isolating regions between the adjacent vertical transistors in the semiconductor substrate comprises forming the isolating regions between the adjacent vertical transistors in the semiconductor substrate from the first side of the semiconductor substrate, and wherein the method further comprises: etching the semiconductor substrate from the second side of the semiconductor substrate to expose the conductive material in the corresponding isolating region, without exposing the vertical gates of the two adjacent vertical transistors (see ¶[0057], ¶[0070]; Figures 7A-7B, Figures 10A-B and Figure 13B).
With respect to claim 5, Sukekawa discloses wherein etching the semiconductor substrate from the second side of the semiconductor substrate comprises: etching the semiconductor substrate in an etching region from a surface of the semiconductor substrate along the vertical direction, wherein the etching region has a bottom edge and an etching depth from the surface of the semiconductor substrate to the bottom edge, and wherein, along the vertical direction, the etching depth is greater than a first distance between the surface of the semiconductor substrate and an end of the conductive material filled in the middle trench and smaller than a second distance between the surface of the semiconductor substrate and an end of the deposited at least one conductive layer in each of the two adjacent trenches (see ¶[0057], ¶[0070]; Figures 7A-7B, Figures 10A-B and Figure 13B).
With respect to claim 6, Sukekawa discloses forming a corresponding conductive interconnection in contact with the exposed conductive material in the corresponding isolating region in the second side of the semiconductor substrate (See ¶[0078] and Figure 13B).
With respect to claim 7, Sukekawa discloses forming a plurality of bit lines [18] from the second side of the semiconductor substrate (See Figure 13B).
With respect to claim 8, Sukekawa discloses wherein the method comprises: depositing the isolating material to fill a portion of each of the plurality of trenches along the vertical direction; patterning photoresist to cover the two adjacent trenches and to expose the middle trench; etching the deposited isolating material in the middle trench; depositing the conductive material in the middle trench to form the corresponding isolating region; and removing the photoresist and depositing the at least one conductive layer on the deposited isolating material in the two adjacent trenches to form the vertical gates of the two adjacent vertical transistors (see Figure 7B and ¶[0058]; selective wet etching).
With respect to claim 9, Sukekawa discloses wherein the method comprises: for each of the two adjacent trenches, cutting the deposited at least one conductive layer in the trench to form two separate vertical gates of a pair of independent vertical transistors in the trench (See ¶[0041]).
With respect to claim 10, Sukekawa discloses forming an array structure in a first region, the array structure comprising a plurality of strings of memory cells, each memory cell of the plurality of strings of memory cells comprising a respective vertical transistor, wherein the isolating regions and the plurality of adjacent vertical transistors in the semiconductor substrate are formed in a second region adjacent to the first region (see ¶[0005]).
With respect to claim 11, Sukekawa discloses wherein forming the array structure comprises: forming the respective vertical transistors of the plurality of strings of memory cells by depositing the at least one conductive layer in corresponding trenches, wherein, along the vertical direction, a length of the deposited at least one conductive layer in the corresponding trenches in the first region is greater than the length of the vertical gate of each of the two adjacent vertical transistors in the second region (See Figure 6B and 14B).
With respect to claim 12, Sukekawa discloses wherein the method comprises: depositing the isolating material to fill a portion of each of the two adjacent trenches for the two adjacent vertical transistors in the second region and the corresponding trenches for the memory cells in the first region along the vertical direction; patterning photoresist to cover the two adjacent trenches and to expose the corresponding trenches; etching the deposited isolating material in the corresponding trenches; removing the photoresist to expose the two adjacent trenches; and depositing the at least one conductive layer on the deposited isolating material in the two adjacent trenches to form the vertical gates of the two adjacent vertical transistors and in the corresponding trenches to form the vertical transistors for the memory cells (see Figure 7B and ¶[0058]; selective wet etching).
With respect to claim 13, Sukekawa discloses a semiconductor device, comprising: a semiconductor substrate [14]; a plurality of vertical transistors [132] positioned in the semiconductor substrate along a horizontal direction, each of the plurality of vertical transistors extending along a vertical direction perpendicular to the horizontal direction (See Figure 6B); and a plurality of isolating regions [85/43] in the semiconductor substrate (see ¶[0043] and ¶[0055]), each of the plurality of isolating regions being between two adjacent vertical transistors of the plurality of vertical transistors along the horizontal direction (See Figure 6B), wherein the isolating region comprises a conductive material (See ¶[0043]), and wherein, along the vertical direction, a length of the conductive material in the isolating region is greater than a length of a vertical gate of each of the two adjacent vertical transistors (see Figure 6B and 14B).
With respect to claim 14, Sukekawa discloses wherein the isolating region comprises the conductive material filled in a middle trench [116] between two adjacent trenches corresponding to the two adjacent vertical transistors, wherein the vertical gate of each of the two adjacent vertical transistors comprises at least one conductive layer on an isolating material filled in a portion of a respective trench of the two adjacent trenches, and wherein, along the vertical direction, a length of the at least one conductive layer in each of the two adjacent trenches is smaller than the length of the conductive material filled in the middle trench (See Figure 12A-B).
With respect to claim 19, Sukekawa discloses a system, comprising: a memory device (See ¶[0005]) comprising: a semiconductor substrate [14]; a plurality of vertical transistors [132] positioned in the semiconductor substrate along a horizontal direction, each of the plurality of vertical transistors extending along a vertical direction perpendicular to the horizontal direction (See Figure 6B); and a plurality of isolating regions [85/43] in the semiconductor substrate (see ¶[0043] and ¶[0055]), each of the plurality of isolating regions being between two adjacent vertical transistors along the horizontal direction (See Figure 6B), wherein the isolating region comprises a conductive material (See ¶[0043]), and wherein, along the vertical direction, a length of the conductive material in the isolating region is greater than a length of a vertical gate of each of the two adjacent vertical transistors; and a controller coupled to the memory device and configured to control the memory device (see Figure 6B and 14B).
With respect to claim 20, Sukekawa discloses wherein the isolating region comprises the conductive material filled in a middle trench [116] between two adjacent trenches corresponding to the two adjacent vertical transistors, wherein the vertical gate of each of the two adjacent vertical transistors comprises at least one conductive layer on an isolating material filled in a portion of a respective trench of the two adjacent trenches, and wherein, along the vertical direction, a length of the at least one conductive layer in each of the two adjacent trenches is smaller than the length of the conductive material filled in the middle trench (See Figure 12A-B).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONATHAN HAN whose telephone number is (571)270-7546. The examiner can normally be reached 9.00-5.00PM PST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, STEVEN LOKE can be reached at 571-272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JONATHAN HAN/Primary Examiner, Art Unit 2818
/STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818