DETAILED ACTION
This Office Action is in response to the applicant's application filed September 28th, 2023. In virtue of this communication, claims 1-20 are currently presented in the instant application.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 9, and 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipate by Morein (US 2021/0111161 A1).
With respect to claim 1, Morein teaches a method in Figs. 1-6 comprising:
forming a plurality of strings of memory cells 110 in a first side of a semiconductor substrate (wafer) along a vertical direction, the semiconductor substrate (wafer) comprising a semiconductor material (see Figs. 1-6 and paragraphs 12, 15, 24, 30);
forming a plurality of alternating stripes of the semiconductor material (410A-410E) and an isolating material (402A-402E) in a second side of the semiconductor substrate (wafer) along a horizontal direction perpendicular to the vertical direction, the second side being opposite to the first side along the vertical direction (see Figs. 1-4 and paragraphs 12, 29, 43, 45); and
forming a plurality of bit lines (BL, 130 in Fig. 1 and 410 in Fig. 4) in the second side of the semiconductor substrate (wafer) (see Figs. 1-4 and paragraphs 31, 32, 42, 43), wherein forming the plurality of bit lines comprises:
depositing a layer of a metallic material 412 on the plurality of alternating stripes of the semiconductor material and the isolating material (see Fig. 4 and paragraphs 32, 44-46); and
forming each bit line of the plurality of bit lines in a corresponding stripe of the semiconductor material of the plurality of alternating stripes by forming a composite conductive material (414A-414E) based on the metallic material 412 and the semiconductor material in the corresponding stripe of the semiconductor material (410A-410E) (see Fig. 4 and paragraphs 12, 32, 42-47).
With respect to claim 2, Morein teaches the method of claim 1, wherein forming the composite conductive material (414A-414E) based on the metallic material 412 and the semiconductor material in the corresponding stripe of the semiconductor material (410A-410E) comprises: annealing the metallic material and the semiconductor material, such that the metallic material reacts with the semiconductor material to form the composite conductive material (414A-414E) (see Fig. 4 and paragraphs 18, 32, 45).
With respect to claim 3, Morein teaches the method of claim 1, wherein the semiconductor material comprises silicon, the isolating material comprises oxide, and the composite conductive material comprises silicide (see Figs. 1-4 and paragraphs 12, 28, 29, 32, 45).
With respect to claim 4, Morein teaches the method of claim 1, further comprising: after forming the plurality of bit lines in the second side of the semiconductor substrate, removing a residue of the metallic material from the second side of the semiconductor substrate (see Fig. 4 and paragraph 45-47).
With respect to claim 5, Morein teaches the method of claim 1, wherein forming the plurality of alternating stripes of the semiconductor material (410A-410E) and the isolating material 402A-402E) in the second side of the semiconductor substrate (wafer) comprises: thinning the semiconductor substrate from the second side of the semiconductor substrate to expose the plurality of alternating stripes of the semiconductor material and the isolating material (see Figs. 1-4 and paragraphs 16, 31, 32), wherein the method further comprises: implanting ions into the second side of the semiconductor substrate, and wherein forming the composite conductive material based on the metallic material and the semiconductor material in the corresponding stripe of the semiconductor material comprises: forming the composite conductive material based on the metallic material and the semiconductor material with the implanted ions (see Figs. 1-4 and paragraphs 17, 35, 42-47).
With respect to claim 9, Morein teaches the method of claim 5, wherein thinning the semiconductor substrate (wafer) from the second side of the semiconductor substrate comprises: etching the semiconductor material in the second side of the semiconductor substrate; and polishing a top surface of the etched semiconductor material in the second side of the semiconductor substrate (see Figs. 1-4 and paragraphs 16, 18, 31, 32, 47).
With respect to claim 16, Morein teaches a semiconductor device in Figs. 1-6, comprising:
a plurality of strings of memory cells 110 in a first side of a semiconductor substrate (wafer) along a vertical direction, the semiconductor substrate (wafer) comprising a semiconductor material (see Figs. 1-6 and paragraphs 12, 15, 24, 30); and
a plurality of bit lines (BL, 130 in Fig. 1 and 410 in Fig. 4) in a second side of the semiconductor substrate (wafer), the second side being opposite to the first side along the vertical direction, wherein adjacent bit lines of the plurality of bit lines (410A-410E) are separated by an isolating material (402A-402E) along a horizontal direction perpendicular to the vertical direction (see Figs. 1-4 and paragraphs 12, 29, 31, 32, 42, 43, 45),
wherein the plurality of bit lines are made of a composite conductive material (414A-414E) that is based on the semiconductor material (of the wafer), and wherein the plurality of bit lines (410A-410E) are on a layer of the semiconductor material with implanted ions (see Fig. 4 and paragraphs 12, 17, 32, 35, 42-47).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6-8, 10-14, and 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Morein (US 2021/0111161 A1) in view of Kumar et al. (US 2019/0027535 A1; hereinafter Kumar).
With respect to claim 6, Morein discloses the method of claim 5.
Morein does not explicitly disclose wherein implanting the ions into the second side of the semiconductor substrate comprises: implanting semiconductor ions into the second side of the semiconductor substrate; implanting N+ type ions into the second side of the semiconductor substrate; and activating the implanted N+ type ions with the implanted semiconductor ions under an activation temperature.
Kumar discloses a similar method wherein implanting the ions into the second side of the semiconductor substrate comprises: implanting semiconductor ions into the second side of the semiconductor substrate; implanting N+ type ions into the second side of the semiconductor substrate; and activating the implanted N+ type ions with the implanted semiconductor ions under an activation temperature (see Figs. 1-11 and paragraphs 40, 69, 97).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that implanting the ions into the second side of the semiconductor substrate of Morein would comprise: implanting semiconductor ions into the second side of the semiconductor substrate; implanting N+ type ions into the second side of the semiconductor substrate as taught by Kumar because such ions are well known in the art and it has been held by the courts that selection of a prior art material on the basis of its suitability for its intended purpose is within the level of ordinary skill (see MPEP 2144.07). Additionally, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the method of Morein would comprise activating the implanted N+ type ions with the implanted semiconductor ions under an activation temperature as taught by Kumar because it is well known in the art that annealing serves to activate the implanted dopants (see Kumar: paragraph 97).
With respect to claim 7, the combination of Morein and Kumar discloses the method of claim 6, wherein the semiconductor material comprises silicon, the semiconductor ions comprise Germanium (Ge) ions, and the N+ type ions comprise arsenic (As) ions or phosphorus (P) ions (see Kumar: paragraphs 40, 69).
With respect to claim 8, the combination of Morein and Kumar discloses the method of claim 6, wherein the activation temperature is lower than a nominal temperature for activating the N+ type ions without implanting the semiconductor ions (see Kumar: paragraph 97; annealing serves to activate implanted dopants).
It is noted that the specification contains no disclosure of either the critical nature of the claimed temperatures or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the Applicant must show that the chosen dimensions are critical (see MPEP 2144.05 III A).
With respect to claim 10, Morein discloses the method of claim 5, wherein each memory cell of the plurality of strings of memory cells 110 comprises a vertical transistor along the vertical direction (see Fig. 1 and paragraphs 13, 14, 24), and wherein forming the plurality of strings of memory cells comprises: forming a gate terminal of the vertical transistor; forming a first terminal of the vertical transistor; and forming a second terminal of the vertical transistor (see Figs. 1, 6, and paragraphs 13-15, 24, 30, 35, 59, 60; note vertical DRAM formed).
Morein does not explicitly disclose wherein the gate terminal is formed by depositing at least one metallic layer on an inner surface of a trench along the vertical direction, or wherein the first terminal is formed by implanting the ions from the first side of the semiconductor substrate, or wherein the second terminal is formed by implanting the ions into the second side of the semiconductor substrate. Morein does disclose that the memory cell storage elements 110 may be built using DRAM memory technologies.
Kumar discloses a similar method wherein a first terminal and a second terminal are formed by implanting ions (see paragraphs 69 and 97).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the method of Morein would comprise the first terminal formed by implanting the ions from the first side of the semiconductor substrate, and the second terminal formed by implanting the ions into the second side of the semiconductor substrate as taught by Kumar because it is well known in the art to form source and drain terminals using ion implantation (see Kumar: paragraphs 69, 97). Additionally, as Morein discloses that the memory cell storage elements 110 may be built using DRAM memory technologies, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the gate terminal would be formed by depositing at least one metallic layer on an inner surface of a trench along the vertical direction because such a configuration is well known in the art that have flown naturally to one of ordinary skill in the art as necessitated by the specific requirements of a given application (see MPEP 2144 I).
With respect to claim 11, the combination of Morein and Kumar discloses the method of claim 10, wherein each of the plurality of bit lines BL is formed on the second terminal of the vertical transistor and is coupled to the second terminal of the vertical transistor (see Morein: Fig. 1 and paragraphs 13, 24, 35).
With respect to claim 12, the combination of Morein and Kumar discloses the method of claim 10, wherein each memory cell of the plurality of strings of memory cells 110 further comprises a capacitor coupled to the vertical transistor, and wherein forming the plurality of strings of memory cells comprises: forming the capacitor before forming the vertical transistor, the capacitor being over the vertical transistor along the vertical direction (see Morein: Fig. 1 and paragraphs 13-15, 24, 30, 58-60. Also note the vertical DRAM obviously consists of a stacked capacitor and transistor, MPEP 2144 I).
With respect to claim 13, the combination of Morein and Kumar discloses the method of claim 10, wherein forming the plurality of strings of memory cells 110 comprises: forming gate terminals of a pair of independent vertical transistors in a same trench along the vertical direction, the gate terminals being separated by an isolating material along a third direction perpendicular to the vertical direction and the horizontal direction (see Figs. 1, 6, and paragraphs 13-15, 24, 30, 35, 59, 60; note vertical DRAM formed). As Morein discloses that the memory cell storage elements 110 may be built using DRAM memory technologies, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that forming the plurality of strings of memory cells 110 would comprise: forming gate terminals of a pair of independent vertical transistors in a same trench along the vertical direction, the gate terminals being separated by an isolating material along a third direction perpendicular to the vertical direction and the horizontal direction because such a configuration is well known in the art that have flown naturally to one of ordinary skill in the art as necessitated by the specific requirements of a given application (see MPEP 2144 I). Additionally, the gate terminals of adjacent vertical transistors are obviously isolated to allow proper device operation (see MPEP 2144 I).
With respect to claim 14, the combination of Morein and Kumar discloses the method of claim 13, further comprising: forming an isolating region between adjacent pairs of independent vertical transistors along the third direction (see Figs. 1, 6, and paragraphs 13-15, 24, 30, 35, 59, 60; note vertical DRAM formed). As Morein discloses that the memory cell storage elements 110 may be built using DRAM memory technologies, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the method would include forming an isolating region between adjacent pairs of independent vertical transistors along the third direction because such a configuration is well known in the art that have flown naturally to one of ordinary skill in the art as necessitated by the specific requirements of a given application (see MPEP 2144 I). Additionally, adjacent vertical transistors are obviously isolated to allow proper device operation (see MPEP 2144 I).
With respect to claim 17, Morein discloses the semiconductor device of claim 16.
Morein does not explicitly disclose wherein the implanted ions comprise semiconductor ions and N+ type ions.
Kumar discloses a similar semiconductor device wherein implanted ions comprise semiconductor ions and N+ type ions (see Figs. 1-11 and paragraphs 40, 69).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the implanted ions of Morein would comprise semiconductor ions and N+ type ions as taught by Kumar because it is well known in the art to dope with semiconductor and N+type ions and it has been held by the courts that selection of a prior art material on the basis of its suitability for its intended purpose is within the level of ordinary skill (see MPEP 2144.07).
With respect to claim 18, Morein discloses the semiconductor device of claim 16, wherein each memory cell of the plurality of strings of memory cells 110 comprises a vertical transistor along the vertical direction (see Fig. 1 and paragraphs 13, 14, 24), and wherein a portion is configured to be a terminal of the vertical transistor and to be conductively coupled to a corresponding bit line BL (see Figs. 1, 6, and paragraphs 13-15, 24, 30, 35, 59, 60; note vertical DRAM connected to bit lines).
Morein does not explicitly disclose wherein the portion is of the layer of the semiconductor material with the implanted ions configured to be a terminal of the vertical transistor.
Kumar discloses a similar semiconductor device wherein a terminal is formed by implanting ions (see paragraphs 69 and 97).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the portion of the layer of the semiconductor material with the implanted ions of Morein would be configured to be a terminal of the vertical transistor based on the combined teachings of Morein and Kumar because it is well known in the art to form source and drain terminals using ion implantation (see Kumar: paragraphs 69, 97).
With respect to claim 19, Morein discloses the semiconductor device of claim 18, wherein gate terminals of a pair of independent vertical transistors are in a same trench along the vertical direction and separated by an isolating material along a third direction perpendicular to the vertical direction and the horizontal direction, and wherein an isolating region is between adjacent pairs of independent vertical transistors along the third direction (see Figs. 1, 6, and paragraphs 13-15, 24, 30, 35, 59, 60; note vertical DRAM). As Morein discloses that the memory cell storage elements 110 may be built using DRAM memory technologies, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that gate terminals of a pair of independent vertical transistors are in a same trench along the vertical direction and separated by an isolating material along a third direction perpendicular to the vertical direction and the horizontal direction, and wherein an isolating region is between adjacent pairs of independent vertical transistors along the third direction because such a configuration is well known in the art that have flown naturally to one of ordinary skill in the art as necessitated by the specific requirements of a given application (see MPEP 2144 I). Additionally, the gate terminals of adjacent vertical transistors are obviously isolated to allow proper device operation (see MPEP 2144 I).
Claims 15 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Morein (US 2021/0111161 A1) in view of Sanuki (US 2020/0286842 A1).
With respect to claim 15, Morein discloses the method of claim 1, wherein the plurality of strings of memory cells and the plurality of bit lines are formed in an array die (see Figs. 1-6 and paragraphs 13, 14, 23, 24, 27).
Morein does not explicitly disclose wherein the method further comprises: integrating a control die with the array die by bonding the first side of the semiconductor substrate with a front side of the control die and conductively coupling one or more conductive lines of the array die to a control circuit in the front side of the control die.
Sanuki discloses a method in at least Fig. 1 wherein the method further comprises: integrating a control die 2 with an array die 1 by bonding a first side of the semiconductor substrate with a front side of the control die and conductively coupling one or more conductive lines of the array die 1 to a control circuit in the front side of the control die 2 (see Fig. 1 and paragraphs 19, 21-23, 27).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the method of Morein would further comprise: integrating a control die with the array die by bonding the first side of the semiconductor substrate with a front side of the control die and conductively coupling one or more conductive lines of the array die to a control circuit in the front side of the control die as taught by Sanuki because it is well known in the art to combine a control die with an array memory die to control the array memory die (see MPEP 2144 I and Sanuki: paragraph 27).
With respect to claim 20, Morein discloses a system in Figs. 1-6, comprising:
a memory device comprising:
an array structure comprising a plurality of strings of memory cells 110 in a first side of a semiconductor substrate (wafer) along a vertical direction, the semiconductor substrate (wafer) comprising a semiconductor material (see Figs. 1-6 and paragraphs 12, 15, 24, 30); and
a plurality of bit lines (BL, 130 in Fig. 1 and 410 in Fig. 4) in a second side of the semiconductor substrate (wafer), the second side being opposite to the first side along the vertical direction, wherein adjacent bit lines of the plurality of bit lines (410A-410E) are separated by an isolating material (402A-402E) along a horizontal direction perpendicular to the vertical direction (see Figs. 1-4 and paragraphs 12, 29, 31, 32, 42, 43, 45), wherein the plurality of bit lines are made of a composite conductive material (414A-414E) that is based on the semiconductor material (of the wafer), and wherein the plurality of bit lines (410A-410E) are on a layer of the semiconductor material with implanted ions (see Fig. 4 and paragraphs 12, 17, 32, 35, 42-47).
Morein does not explicitly disclose a controller coupled to the memory device and configured to control the memory device.
Sanuki discloses a system in at least Fig. 1 comprising a controller 2 coupled to a memory device 1 and configured to control the memory device 1 (see Fig. 1 and paragraphs 19, 21-23, 27).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the system of Morein would comprise a controller coupled to the memory device and configured to control the memory device as taught by Sanuki because it is well known in the art to combine a controller with a memory device to control the memory device (see MPEP 2144 I and Sanuki: paragraph 27).
Inquiry
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JORDAN M KLEIN whose telephone number is (571)270-7544. The examiner can normally be reached 9:00 am - 5:00 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at 571-272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/J.M.K/Examiner, Art Unit 2893
/SUE A PURVIS/ Supervisory Patent Examiner, Art Unit 2893
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