DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Domestic Benefit
Present application 18/477,521 filed 09/28/2023 is a continuation of PCT/CN2023/114355 filed 08/23/2023.
Foreign Priority
No claim to an application for foreign priority.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 03/14/2025 was filed before first Office action. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has been considered.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title or similar is suggested:
-- MEMORY DEVICES HAVING VERTICAL TRANSISTORS IN PERIPHERAL CIRCUITS WITH CORRESPONDING INTERCONNECTS BETWEEN VERTICAL TRANSISTORS AND MEMORY CELLS --.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 defines a singular array reciting “a first array of memory cells” then immediately recites with “each…array.” This is entirely unclear due the singular versus plural nature of an array(s). Therefore, it is unclear how the first vertical transistor is connected to other elements in the claim. It is further unclear how the second vertical transistor is connected to the memory cells.
Claim 1 with the expression “each of the first array of memory cells comprises a first vertical transistor and a storage structure coupled to the first vertical transistor in a first direction” reads that each-- thus all-- memory cells comprise a (same) first vertical transistor and a (same) storage structure, this being in contradiction with the description (see Figure 2A). According to the description (see Figure 2A), each memory cell of the first array of memory cells comprises a corresponding first vertical transistor and a corresponding storage structure coupled to the corresponding first vertical transistor in a first direction. For sake of clarity, claim 1 should be drafted accordingly.
In the limitation "a second vertical transistor coupled to one of the first array of memory cells through the first vertical transistor of the one of the first array of memory cells" of claim 1, “the first vertical transistor” is not clear since it has no antecedent basis, a plurality of first vertical transistors being previously established. Furthermore, it is not clear how a transistor can be coupled to a memory cell comprising a first vertical transistor through the first vertical transistor since the latter is included in the memory cell. According to the description (see Figures 2A-2B), second vertical transistor coupled to a corresponding memory cell of the first array of memory cells.
The same objection applies to claim 6 "each comprising a third vertical transistor" which should be replaced by "each comprising a corresponding third vertical transistor".
Dependent claims 2-12 do not remedy the indefiniteness of claim 1 and are rejected for incorporating the indefiniteness from the independent claim.
Independent claim 13 has similar clarity issue as independent claim 1 with respect to array versus arrays and thereby the corresponding interconnections to the memory. This claim is general unclear for the same reasons as independent claim 1
Dependent claim 14 does not remedy the indefiniteness of claim 13 and is rejected for incorporating the indefiniteness from the independent claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 6 and 13-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2021/0028176 A1 to Derner et al. (“Derner”).
Regarding independent claim 1, Derner teaches in Figures 2-3 of a semiconductor device (as defined below), comprising:
a first array of memory cells (216-1, 312-1), wherein each memory cell of the first array of memory cells comprises a corresponding first vertical transistor (325) and a corresponding storage structure (327) coupled to the corresponding first vertical transistor in a first direction (Z direction) (see also [0033] “Each respective memory cell 312 can include a capacitor 327 and a vertical TFT 325 that can be coupled between the capacitor 327 and a respective digit line 318”); and
a first peripheral circuit (local sense amplifier 220, 320) adjacent to the first array (312-1) of memory cells in a second direction (Y direction) perpendicular to the first direction (Z direction), wherein the first peripheral circuit (220, 320) comprises a second vertical transistor (357-1, see [0038] "Sense amplifier 320 includes vertical TFTs 357-1 and 357-2 (e.g., that can be referred to as vertical sense amplifier TFTs) at vertical level 360") coupled to one of the first array of memory cells through the first vertical transistor (325) of the one a corresponding memory cell of the first array of memory cells (via digit line 318-1, see fig.3).
Regarding claim 2, Derner teaches (see Figure 3 and Figure 4), the first semiconductor body being the pillar 422, the first gate structure being 415, 419 of the access transistor 325, the second semiconductor body being the 422, the second gate structure 415, 419 of 357-1.
Regarding claim 3, Derner teaches of first conductive layer (415), first gate dielectric layer (419), first terminal (426-1) and second terminal 426-1 of fig.4 for transistor 325 of Figure 3, see also [0045].
Regarding claim 6, Derner teaches in Figure 3, the first and second array being on the sides of the local sense amplifier 320. As explained in claim 1 rejection, supra there are a plurality of vertical transistors.
Compared to claim 1, independent claim 13 adds a first array region comprising the first array and a circuit region adjacent to the first array region, the vertical transistors extending along the first direction, removing the feature of the storage structure. These features are all disclosed by Derner in Figures 2-3. The peripheral circuit because it is a circuit is thereby in a circuit region.
Regarding claim 14, refer to claim 6 rejection supra.
Regarding independent claim 15, Derner teaches a method for forming a semiconductor device, comprising:
forming a first semiconductor body (422 of Figure 4A for 325 of Figure 3, see Figure 4A disclosing a vertical TFT, [0045] “a portion 422 of a vertical semiconductor structure 424 that can be polysilicon (e.g., polycrystalline silicon)") of a first vertical transistor (325) in a first region (312-1, 216-1) of a semiconductor layer and a second semiconductor body (422 of fig.4A for 357-1 of Figure 3) of a second vertical transistor (357-1) in a second region (corresponding to sense amplifier 320) adjacent to the first region of the semiconductor layer, wherein the first semiconductor body and the second semiconductor body are formed on a first side of the semiconductor layer (see Figure 3, [0109] “Furthermore, when reference is made to a semiconductor in the preceding description, previous process steps may have been utilized to form regions/junctions in the base semiconductor structure, and the term semiconductor can include the underlying materials containing such regions/junctions”);
forming a first gate structure (415, 419 of Figure 4A for 325 of Figure 3, see [0045] “Gate 415 can wrap completely around a gate dielectric 419 that can wrap completely around a portion 422 of a vertical semiconductor structure 424”) of the first vertical transistor (325) and a second gate structure (415, 419 of Figure 4A for 357-1 of Figure 3) of the second vertical transistor (357-1), wherein the first gate structure is in contact with at least one side of the first semiconductor body, the second gate structure is in contact with at least one side of the second semiconductor body (see Figures 4A-B); and
forming a first storage structure (327) above and in contact with a first end of the first semiconductor body (see also [0033] “Each respective memory cell 312 can include a capacitor 327 and a vertical TFT 325 that can be coupled between the capacitor 327 and a respective digit line 318”).
Regarding claim 16, Derner teaches of third semiconductor body and third gate structure of 357-2 of Figure 3.
Claims 1-3 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by IDS provided JP 2013062350A
Regarding independent claim 1, the Japanese patent application teaches of a semiconductor device (as defined below), comprising:
a first array of memory cells (in region 1), wherein each memory cell of the first array of memory cells comprises a corresponding first vertical transistor (the vertical transistor in region 1) and a corresponding storage structure (capacitor connected to 136, [0024] “When the semiconductor device 100 is applied to a DRAM, a capacitor (not shown) and an upper electrode, if necessary, are formed on the contact plugs 56a and 56b of the semiconductor device 100”) coupled to the corresponding first vertical transistor in a first direction (in the vertical direction of fig.2); and
a first peripheral circuit adjacent (2) to the first array of memory cells in a second direction (horizontal) perpendicular to the first direction (vertical), wherein the first peripheral circuit comprises a second vertical transistor (see region 2) coupled to one a corresponding memory cell of the first array of memory cells (via bit line 18a, see [0024] “the lower diffusion layers 18a and 18b serving as the bit line”).
Regarding claim 2, the Japanese patent teaches of (see Figure 2), the first semiconductor body being the pillar 11a, the first gate structure being 22a, 25a of the access transistor in region 1, the second semiconductor body being the 11b, the second gate structure 22b, 25b);
Regarding claim 5, the Japanese patent teaches of channel lengths in fig. 2 between the peripheral vertical transistors in region 2 and the memory cell vertical transistors in region 1, see also [0044].
Allowable Subject Matter
Claims 4 and 7-12 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Claim 4 contains allowable subject matter, because the closest art of record, singularly or in combination, fails to disclose or suggest, in combination with the other elements of claim 4, the second gate structure comprises a second conductive layer and a second gate dielectric layer disposed between the second conductive layer and the second semiconductor body in the second direction; and width of the first gate dielectric layer is different from width of the second gate dielectric layer in the second direction.
Claim 7 contains allowable subject matter, because the closest art of record, singularly or in combination, fails to disclose or suggest, in combination with the other elements of claim 7, wherein the first peripheral circuit comprises at least a portion of a sense amplifier, the sense amplifier comprises a latch circuit, and the latch circuit comprises the second vertical transistor.
IDS provided reference number 2, teaches a similar limitations in Figures 3I-3J with respect to a sense amplifier. However, the combination of Derner with reference number 2 or the combination of the Japanese patent application with reference number 2 is impermissible hindsight.
Dependent claims 8-11 contain allowable subject matter, because they depend on the allowable subject matter of claim 7.
Claim 12 contains allowable subject matter, because the closest art of record, singularly or in combination, fails to disclose or suggest, in combination with the other elements of claim 12, further comprising a second peripheral circuit comprising a planar transistor, wherein the second peripheral circuit is coupled to the first array of memory cells and the first peripheral circuit.
Claims 17-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 17 contains allowable subject matter, because the closest art of record, singularly or in combination, fails to disclose or suggest, in combination with the other elements of claim 17, doping the semiconductor layer in the first region with a P type dopant; doping the semiconductor layer in a first part of the second region with the P type dopant to form the second semiconductor body; and doping the semiconductor layer in a second part of the second region with an N type dopant to form the third semiconductor body.
Claim 18 contains allowable subject matter, because the closest art of record, singularly or in combination, fails to disclose or suggest, in combination with the other elements of claim 18, removing a portion of the semiconductor layer from a second side to expose a second end of the first semiconductor body opposite to the first end of the first semiconductor body, a first end of the second semiconductor body, and a first end of the third semiconductor body; and forming a first bit line in contact with the second end of the first semiconductor body, a second end of the second semiconductor body, and a second end of the third semiconductor body, wherein the first end of the second semiconductor body is coupled to a fourth vertical transistor, and wherein the first end of the third semiconductor body coupled to a fifth vertical transistor.
Claim 19 contains allowable subject matter, because the closest art of record, singularly or in combination, fails to disclose or suggest, in combination with the other elements of claim 19, forming a fourth semiconductor body of a sixth vertical transistor in a third region, the second region is between the first region and the third region; forming a fourth gate structure in contact with at least one side of the fourth semiconductor body; and forming a second storage structure above and in contact with a first end of the fourth semiconductor body.
Dependent claim 20 contains allowable subject matter, because it depends on the allowable subject matter of claim 19.
Conclusion
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27 December 2025
/John P. Dulka/Primary Examiner, Art Unit 2817