DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group II, claims 7-12 in the reply filed on 02/03/2026 is acknowledged.
Claim Objections
Claim 10 is objected to because of the following informalities: Claim is dependent on claim 6, based on language of “the method according to claim 6,” it appears that this is in error and should be dependent on claim 7. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 10 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
With respect to claim 10, the recitation of “after depositing a sacrificial layer on the top face of the metal pad, then removing the sacrificial layer to expose the top face of the metal pad” renders the claim as indefinite. It is unclear as to whether depositing an insulating material over the entire surface of the electronic chip occurs after depositing a sacrificial layer on the top face of the metal pad or whether “depositing an insulating material” occurs and then “after depositing a sacrificial layer, then removing the sacrificial layer occurs.”
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 7-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Daubenspeck et al. (U.S. Publication No. 2008/0194095 A1; hereinafter Daubenspeck) in view of Lin et al. (U.S. Publication No. 2013/0069225 A1; hereinafter Lin) and Wu et al (U.S. Publication No. 2007/0087546 A1)
With respect to claim 7, Daubenspeck discloses a method of manufacturing an electronic chip according to claim 1, including the following successive steps: a) on one face of a substrate [10’], successively depositing a first metal layer [21’] (TiW) on, and in contact with, said face of the substrate, an electrically conductive barrier layer on [22’] (Cr-Cu), and in contact with, said first metal layer, and a second metal layer [30] (Cu) on, and in contact with, said electrically conductive barrier layer (See Figure 2B); b) etching the first metal layer, the electrically conductive barrier layer, and the second metal layer so that a metal pad is defined (See Figure 2C-3A, final orientation of the metal pad includes [40’],[70’] Fig. 5C); c) forming an electrically insulating barrier layer [12’] on, and in contact with, the sidewall of the first metal layer around the entire periphery of the metal pad (See Figure 5C).
Daubenspeck fails to disclose a semiconductor substrate or that the metal pad is defined by means of a single photolithography step. In the same field of endeavor, Lin teaches a semiconductor substrate [122] (see4 ¶[0038]). Additionally, Wu teaches etching the first metal layer [38], the electrically conductive barrier layer [40], and the second metal layer [42] so that a metal pad [36] is that the metal pad is defined by means of a single photolithography step (See Figure 10-11; ¶[0019]). Implementation of a semiconductor substrate as taught by Lin is well appreciated in the art as the techniques of Daubenspeck can be utilized to provide contact structures to semiconductor chip structures (See Lin ¶[0038]). Furthermore, implementation of a single photolithographic step to etch all layers of the metal pad, as taught by Wu simplifies the processing steps to allow for all etching to occur in a single step, thereby controlling the height of the metal pad (See Wu ¶[0019]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 8, the combination of Daubenspeck, Lin and Wu discloses including, prior to step a), a step of depositing a passivation layer on the top face of the substrate, and wherein the electrically insulating barrier layer of step c) is formed by extending the etching of step b) into the passivation layer (see Daubenspeck Figure 5C), and redepositing the etching material on the sidewalls of the metal pad (see Lin Figures 3i-3j). Implementation of redeposition of the etching material as taught by Lin allows for increased support around metal pads (see Lin ¶[0056]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 9, the combination of Daubenspeck, Lin and Wu discloses wherein step c) comprises a step of depositing an insulating material [12’] over the entire surface of the chip, and a step of unidirectional etching so that said insulating material is kept only on the sidewalls of the metal pad to form the electrically insulating barrier layer (see Daubenspeck Figure 5C).
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Daubenspeck in view of Lin and Wu as applied to claim 7 above, and further in view of Gu et al. (U.S. Publication No. 2011/0012239 A1; hereinafter Gu)
With respect to claim 10, the combination of Daubenspeck, Lin and Wu fails to disclose wherein step c) comprises depositing an insulating material over the entire surface of the electronic chip, after depositing a sacrificial layer on the top face of the metal pad, then removing the sacrificial layer to expose the top face of the metal pad, and maintaining the insulating material on the sidewalls of the metal pad so that the barrier layer is formed.
In the same field of endeavor, Gu teaches step c) comprises depositing an insulating material [770] over the entire surface of the electronic chip, after depositing a sacrificial layer [780] on the top face of the metal pad, then removing the sacrificial layer to expose the top face of the metal pad, and maintaining the insulating material on the sidewalls of the metal pad so that the barrier layer is formed (See Figure 7F). Implementation of a sacrificial layer as taught by Gu allows for the metal pad structure to maintain structural integrity while allowing for bulk processing of the insulating material (See ¶[0046]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Daubenspeck in view of Lin and Wu as applied to claim 7 above, and further in view of Nanba (U.S. Publication No. 2012/104602 A1)
With respect to claim 11, the combination of Daubenspeck, Lin and Wu fails to disclose wherein step c) comprises a step of depositing an insulating material over the entire surface of the electronic chip so that the metal pad, and the top face of the substrate are covered, followed by a planarization step intended to uncover the top face of the metal pad. In the same field of endeavor, Nanba teaches a step of depositing an insulating material [6/7] over the entire surface of the electronic chip so that the metal pad, and the top face of the substrate are covered (see Figure 4E), followed by a planarization step intended to uncover the top face of the metal pad (see Figure 4F). Implementation of a planarization step allows for all adjacent metal pads to align in height, allowing for proper connectivity in subsequent mounting of the semiconductor device (See Nanba Figure 4G). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Daubenspeck in view of Lin and Wu as applied to claim 7 above, and further in view of Gu and Solo de Zaldivar (U.S. Publication No. 2006/0278982 A1)
With respect to claim 12, the combination of Daubenspeck, Lin and Wu fails to disclose wherein step c) comprises a step of depositing an insulating material over the entire surface of the electronic chip, a step of depositing a sacrificial layer over the entire surface of the electronic chip, a step of plasma etching the entire surface of the electronic chip so that the top face of the insulating material is exposed opposite the metal pad, a step of ion etching the entire surface of the electronic chip so that the top face of the metal pad is exposed, and finally a step of removing what remains of the sacrificial layer by wet etching. In the same field of endeavor, Gu teaches wherein step c) comprises a step of depositing an insulating material [770] over the entire surface of the electronic chip, a step of depositing a sacrificial layer [780] over the entire surface of the electronic chip, a step of etching the entire surface of the electronic chip so that the top face of the insulating material is exposed opposite the metal pad (See Figure 7E), a step of etching the entire surface of the electronic chip so that the top face of the metal pad is exposed (see Figure 7E), and finally a step of removing what remains of the sacrificial layer by wet etching (See Figure 7F; ¶[0042-0047]). Solo de Zaldivar teaches plasma etching and ion etching to perform the etching to expose the insulating material and the top face of the metal pad (see ¶[0035]). Implementation of a masking and etching process as taught by Gu allows for maintaining structural integrity while allowing for bulk processing of the insulating material (See Gu ¶[0046]). Additionally, substitution of Gu’s wet etching for plasma and ion etching of Solo de Zaldivar allows for high aspect ratio removal and controlled termination of the process to allow for the desired insulation thickness to remain (See Solo de Zaldivar ¶[0035]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
Conclusion
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/JONATHAN HAN/Primary Examiner, Art Unit 2818