DETAILED ACTION
This action is responsive to the application No. 18/477,635 filed on September 29, 2023.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgment
The amendment filed on 06/16/2026 responding to the Office action mailed on 03/17/2026, has been entered. The present Office action is made with all the suggested amendments being fully considered. Claims 6 and 12-14 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a non-elected species, there being no allowable generic or linking claim. Accordingly, pending in this Office action are claims 1 and 3-17.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-5, 7-9, 11, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Yamada (US 2017/0117201) in view of Cruz (US 2007/0114352) and further in view of Choi (US 2020/0176342).
Regarding Claim 1, Yamada (see, e.g., Figs. 1A-1B), teaches a semiconductor module, comprising:
a stacked substrate 12 including an insulating plate 12a, and first and second circuit boards 12b/12c arranged on an upper surface of the insulating plate 12 (see, e.g., pars. 0027, 0029);
a semiconductor element 14 arranged on an upper surface of the first circuit board 12b (see, e.g., par. 0027); and
a metal wiring board 16 having a first bonding portion 16a that is bonded to an upper surface of the semiconductor element 14 via a first bonding material 15 (see, e.g., par. 0031),
wherein:
the first bonding portion 16a includes a first plate-shaped portion having an upper surface and a lower surface opposite to each other.
Yamada does not teach that the first plate-shaped portion has at the lower surface thereof, a boss protruding toward the semiconductor element, and at the upper surface thereof, a first recess at a position corresponding to a position immediately above the boss; and a plurality of second recesses at the upper surface of the first plate-shaped portion, each of the plurality of second recesses has an opening area smaller than an opening area of the first recess, and the lower surface of the first bonding portion excluding an area where the boss is formed is flat.
Cruz (see, e.g., Figs. 2, 9), in similar modules to Yamada, on the other hand, teaches that the first plate-shaped portion 14 has at the lower surface thereof, a boss 114(b) protruding toward the semiconductor element 16, and at the upper surface thereof, a first recess 114(a) at a position corresponding to a position immediately above the boss 114(b), and the lower surface of the first bonding portion (i.e., bonding portion of 14) excluding an area (i.e., area between elements 114(b)) where the boss 114(b) is formed is flat, to provide consistent spacing between the bottom surface of the major portion 14(a) of the source clip structure 14 and the first surface 16(a) of the semiconductor die 16. Because there is a consistent spacing between the major portion 14(a) of the clip structure 14 and the first surface 16(a) of the semiconductor die, a consistent amount of solder is always present between them. Excess solder, if any, can squeeze out from between the clip structure 14 and the semiconductor die 16. In addition to providing for the more consistent solder deposition, the pedestals 14(a)-1 also provide for a larger attachment surface area for the clip structure 14, thereby providing for a better bond and better electrical connection between the source clip structure 14 and the semiconductor die 16. The pedestals 14(a)-1 also prevent the clip structure 14 from undesired "tilting". If the pedestals 14(a)-1 were not present, the clip could "tilt", thereby resulting in the uneven application of solder to the top surface of the semiconductor die 16 (see, e.g., Cruz, par. 0047). Choi (see, e.g., Fig. 9), on the other hand, taches a plurality of second recesses at the upper surface of the first plate-shaped portion, such that the sealing material 150 penetrates the hollow parts of the engraved pattern formed on the upper surface of the clip 160 so that an adhesive force between the clip 160 and the sealing material 150 also increases and micro-moisture may be prevented from penetrating from the outside of a semiconductor package. Therefore, internal corrosion of a semiconductor package may be prevented and thereby, electrical quality and reliability of a semiconductor package may be improved (see, e.g., Choi, pars. 0011, 0048).
It would have been obvious to one of ordinary skill in the art at the time of filing to include in Yamada’s device, the first plate-shaped portion having at the lower surface thereof, a boss protruding toward the semiconductor element, and at the upper surface thereof, a first recess at a position corresponding to a position immediately above the boss; and a plurality of second recesses at the upper surface of the first plate-shaped portion, as taught by Cruz and Choi, to provide consistent spacing between the bottom surface of the major portion of the source clip structure and the first surface of the semiconductor die, thus, providing a consistent amount of solder between them, to provide for a larger attachment surface area for the clip structure, thereby providing for a better bond and better electrical connection between the source clip structure and the semiconductor die, and to prevent the clip structure from undesired "tilting", and to increase an adhesive force between the clip and the sealing material so that micro-moisture may be prevented from penetrating from the outside of a semiconductor package. Therefore, internal corrosion of a semiconductor package may be prevented and thereby, electrical quality and reliability of a semiconductor package may be improved.
The claim limitation that each of the plurality of second recesses has an opening area smaller than an opening area of the first recess, is merely considered a change in the size of the opening area of the first recess 114(a) in Cruz’ device and/or the opening area of the plurality of second recesses P in Choi’s device. The specific claimed size, absent any criticality, is only considered to be an obvious modification of the size of the opening area of the first recess 114(a) in Cruz’ device and/or the opening area of the plurality of second recesses P in Choi’s device, as the courts have held that changes in size without any criticality, are within the level of skill in the art. According to the courts, a particular size is nothing more than one among numerous sizes that a person having ordinary skill in the art will find obvious to provide using routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Accordingly, since the applicant has not established the criticality (see next paragraph below) of the claimed size of the opening area of the first and second recesses, it would have been obvious to one of ordinary skill in the art at the time of filing to have the claimed sizes in Yamada’s/Cruz’/Choi’s the device.
CRITICALITY
The specification contains no disclosure of either the critical nature of the claimed sizes or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen size or upon another variable recited in a claim, the applicant must show that the chosen size is critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Regarding Claim 3, Yamada, Cruz, and Choi teach all aspects of claim 1. They are silent with respect to the claim limitation that a surface roughness of the lower surface of the first plate-shaped portion is less than a surface roughness of the upper surface of the first plate-shaped portion.
However, this claim limitation is merely considered a change in the surface roughness of the lower and/or upper first plate-shaped portions in Yamada’s/Cruz’/Choi’s device.
See also the comments stated above in claim 1 regarding criticality which are considered repeated here.
Regarding Claim 4, Yamada, Cruz, and Choi teach all aspects of claim 1. They are silent with respect to the claim limitation that at the upper surface of the first plate-shaped portion, the opening area of each of the plurality of second recesses has a size in range of 0.5% to 75% of a size of the opening area of the boss or the first recess.
However, this claim limitation is merely considered a change in the size of the opening area of the first and/or second recesses in Yamada’s/Cruz’/Choi’s device.
See also the comments stated above in claim 1 regarding criticality which are considered repeated here.
Regarding Claim 5, Yamada, Cruz, and Choi teach all aspects of claim 1. They are silent with respect to the claim limitation that in a direction from the upper surface toward the lower surface of the first plate-shaped portion, a depth of each of the plurality of second recesses is less than a depth of the first recess.
However, this claim limitation is merely considered a change in the depth of the first and/or second recesses in Yamada’s/Cruz’/Choi’s device.
See also the comments stated above in claim 1 regarding criticality which are considered repeated here.
Regarding Claim 7, Yamada, Cruz, and Choi teach all aspects of claim 1. Choi (see, e.g., Figs. 3(a)-3(b)), teaches that the upper surface of the first plate-shaped portion has an annular protrusion 1a surrounding a corresponding one of the plurality of second recesses P (see, e.g., par. 0039).
Regarding Claim 8, Yamada, Cruz, and Choi teach all aspects of claim 1. Choi (see, e.g., Figs. 4(a)-4(b)), teaches that the upper surface of the first plate-shaped portion has a plurality of annular protrusions 1a respectively surrounding respective ones of the plurality of second recesses P, the upper surface of the first plate-shaped portion having a flat portion between at least an adjacent two of the plurality of annular protrusions 1a (see, e.g., Fig. 4(b)).
Regarding Claim 9, Yamada, Cruz, and Choi teach all aspects of claim 1. Yamada (see, e.g., Figs. 1A-1B), teaches, a sealing resin 18 that seals the stacked substrate 12, the semiconductor element 14, and the metal wiring board 16, wherein the sealing resin 18 covers an upper surface of the first bonding portion 16a and Cruz (see, e.g., Figs. 1, 2, 9), and Choi (see, e.g., Fig. 9), teach that the resin 20(150) fills the first recess 114(a) and the plurality of second recesses P.
Regarding Claim 11, Yamada, Cruz, and Choi teach all aspects of claim 1. Choi (see, e.g., Fig. 2(h)), teaches that the plurality of second recesses P are arranged in a staggered manner.
Regarding Claim 17, Yamada, Cruz, and Choi teach all aspects of claim 1. Yamada/Cruz/Choi disclose the boss, the first recess and the plurality of second recesses. They are silent with respect to the claim limitation that the method comprises pressing a metal plate to form the boss, the first recess and the plurality of second recesses, thereby to manufacture the metal wiring board.
However, note that a “product-by-process” claim is directed to the product per se, no matter how actually made. See In re Thorpe et al., 227 USPQ 964 (CAFC, 1985) and the related case law cited therein which make it clear that it is the final product per se which must determine in a “product-by-process” claim, and not the patentability of the process, and that, as here, an old or obvious product produced by a new method is not patentable as a product, whether claimed in “product-by-process” claim or not. As stated in Thorpe, even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. In re Brown, 459 F.2d 531, 535, 173 USPQ 685, 688 (CCPA 1972); In re Pilkington, 411 F.2d 1345, 162 USPQ 145 (CCPA 1969); Buono v. Yankee Maid Dress Corp., 77 F.2d 274, 279, 26, USPQ 57, 61 (2d. Cir 1935).
NOTE that the applicant has burden of proof in such cases as the above case law makes clear.
In reference to the claimed process step “pressing a metal plate to form the boss, the first recess and the plurality of second recesses, thereby to manufacture the metal wiring board”, this is considered an intermediate method step that does not affect the structure of the final device.
As to the grounds of rejection under section 103, see MPEP §2113 which discusses the handling of “product-by-process” claims and recommends the alternative (§ 102/§ 103) grounds of rejection.
Allowable subject matter
Claims 10, 15, and 16 are allowed.
Response to Arguments
Applicant's arguments filed on 06/16/2026 have been fully considered but they are not persuasive.
The Applicants argue:
Yamada, Cruz, and Choi cannot be read together to teach that “the lower surface of the first bonding portion excluding an area where the boss is formed is flat”.
The examiner responds:
Cruz (see, e.g., Figs. 2, 9), clearly teaches that the lower surface of the first bonding portion 14 excluding an area (i.e., area between elements 114(b)) where the boss 114(b) is formed is flat.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Nelson Garces whose telephone number is (571) 272-8249. The examiner can normally be reached on Mon-Fri 9:00 AM-5:30 PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Wael Fahmy can be reached on (571) 272-1705.
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/Nelson Garces/Primary Examiner, Art Unit 2814
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