Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I, Species I, Subspecies A (claims 1-7) in the reply filed on 13 March 2026 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3, and 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (Pub. No. US 20060214293A1), hereinafter referred to as Park, in view of Chen et al. (US Patent No. 9,159,686), hereinafter referred to as Chen.
Regarding claim 1, Park teaches a method of fabricating a semiconductor package, the method comprising: forming a first insulating film on a semiconductor chip (Fig. 1, semiconductor chip 111, first insulating film 115; ¶6-10); forming a redistribution layer on the first insulating film (Fig. 1, seed metal layer 117, redistribution line 123; ¶6-10); forming a solder crack control part, capable of controlling crack defects of a solder ball, on at least a portion of the redistribution layer (Fig. 2, bump land 223a, metal post 227; ¶6-10); forming a second insulating layer on the redistribution layer and at least a portion of the first insulating film to expose a portion of the redistribution layer and the solder crack control part (Fig. 2, second insulating layer 225; ¶6-10); and forming a solder ball on the redistribution layer exposed and the solder crack control part (Fig. 2, solder bump 229; ¶6-10).
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However, Park does not explicitly teach a top surface level of the solder crack control part being formed to be relatively higher than a top surface level of the second insulating film.
Chen teaches a top surface level of the solder crack control part being formed to be relatively higher than a top surface level of the second insulating film (Fig. 1, crack stopper 116; Col. 7, line 58 – Col. 8, line 37).
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Park and Chen are analogous art as they are in the same field of endeavor of wafer level chip scale packaging. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Park to incorporate the teachings of Chen to have the top surface level of the solder crack control part being formed to be relatively higher than the top surface level of the second insulating film. For the purpose of shaping the solder crack control part to better intercept and stop cracks, as recognized by Chen.
Regarding claim 3, Park further teaches the forming of the redistribution layer comprising: forming a redistribution seed layer on the first insulating film (Fig. 5B, seed metal layer 17, first insulating layer 15; ¶50); forming a space where the redistribution layer is to be formed by applying a photoresist film on the seed layer, followed by sequentially performing an exposure process and a development process (Fig. 5C, photoresist layer 21, open area 21a; ¶51); forming the redistribution layer on the redistribution seed layer exposed (Fig. 5D, redistribution line 23, exposed portion 17a of the seed metal layer 17; ¶52); and removing the photoresist film after forming the redistribution layer (Fig. 5E, photoresist layer 21; ¶52).
Regarding claim 5, Park further teaches the method of claim 3, further comprising, after removing the photoresist film, removing at least a portion of the exposed redistribution seed layer (Fig. 5F, seed metal layer 17; ¶53).
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Chen as applied to claim 1 above, and further in view of Furuya et al. (Pub. No. JP2001053184A), hereinafter referred to as Furuya.
Regarding claim 2, Park does not teach the solder crack control part being formed with a thickness twice or more a thickness of the second insulating film formed on the redistribution layer.
Chen teaches the thickness of the solder crack control part being greater than 20μm (Fig. 1, crack stopper 116; Col. 4, lines 25-31).
Furuya teaches the thickness of the second insulating film being 10μm or less (Fig. 6, second insulating layer 68; ¶10).
Park, Chen, and Furuya are all analogous art as they are all in the same field of endeavor of chip scale packages. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Park to incorporate the teachings of Chen to have the solder crack control part be greater than 20μm in thickness. For the purpose of shaping the solder crack control part to better intercept and stop cracks, as recognized by Chen. It would have also been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Park in view of Chen to incorporate the teachings of Furuya to have the thickness of the second insulating film be 10μm or less. For the purpose of reducing manufacturing costs as recognized by Furuya. Thereby having the solder crack control part being formed with a thickness twice or more a thickness of the second insulating film formed on the redistribution layer.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Chen as applied to claim 3 above, and further in view of Jeong et al. (Pub. No. US20050282315A1), hereinafter referred to as Jeong.
Regarding claim 4, Park in view of Chen does not explicitly teach the forming of the solder crack control part comprising: forming a space where the solder crack control part is to be formed by applying a photoresist film on the redistribution layer, followed by sequentially performing an exposure process and a development process; forming the solder crack part on the exposed redistribution layer; and removing the photoresist film after forming the solder crack control part.
Jeong teaches the forming the solder crack control part comprising: forming a space where the solder crack control part is to be formed by applying a photoresist film on the redistribution layer, followed by sequentially performing an exposure process and a development process (Figs. 12 and 13, I/O terminal 203, seed layer 205, photoresist pattern 208; ¶47-48); forming the solder crack control part on the exposed redistribution layer (Fig. 14, three-dimension pillar-shaped UBM 210; ¶49); and removing the photoresist film after forming the solder crack control part (Fig. 15, photoresist pattern 208; ¶50).
Park, Chen, and Jeong are all analogous art as they are all in the field of endeavor of semiconductor packaging and preventing damage to the solder bumps. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Park in view of Chen to use the method of Jeong to form the solder crack control part on the redistribution layer. For the purpose of simplifying manufacturing by forming the solder crack control part on the redistribution layer using common photolithographic methods.
Claim(s) 6 and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Chen as applied to claim 1 above, and further in view of Lee et al. (US Patent No. 7,830,017), hereinafter referred to as Lee.
Regarding claim 6, Park in view of Chen does not explicitly teach the forming of the second insulating film comprising coating the second insulating film on the first insulating film exposed and at least a portion of the redistribution layer by using a mask.
Lee teaches the forming of the second insulating film comprising coating the second insulating film on the first insulating film exposed and at least a portion of the redistribution layer by using a mask (Figs. 6E & 6F, second insulating layer 240, first insulating layer 220, first metal layer 225, second metal layer 235, sacrificial layer 220; Col. 6, line 32 – Col. 7, line 8).
Park, Chen, and Lee are all analogous art as they are in the same field of endeavor of wafer level chip scale packaging. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Park in view of Chen to use the method of Lee to form the second insulating film. For the purpose of simplifying manufacturing by forming the second layer using common photolithographic methods.
Regarding claim 7, Park in view of Chen does not explicitly teach the forming of the second insulating film comprising: forming a space where the second insulating film is to be formed by applying a photoresist film on the redistribution layer and at least a portion of the solder crack control part, followed by sequentially performing an exposure and development process; forming the second insulating layer on the exposed first insulating film and redistribution layer; and removing the photoresist film after forming the second insulating film.
Lee teaches the forming of the second insulating film comprising: forming a space where the second insulating film is to be formed by applying a photoresist film on the redistribution layer, followed by sequentially performing an exposure and development process (Fig. 1, redistribution line metal layer 125; Col. 1, lines 40-67); forming the second insulating layer on the exposed first insulating film and redistribution layer (Fig. 1, second insulating layer 130, first insulating film 120, redistribution line metal layer 125; Col. 1, lines 40-67); and removing the photoresist film after forming the second insulating film (Col. 1, lines 40-67).
Park, Chen, and Lee are all analogous art as they are in the same field of endeavor of wafer level chip scale packaging. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Park in view of Chen to use the method of Lee to form the second insulating film. For the purpose of simplifying manufacturing by forming the second layer using common photolithographic methods.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Huang et al. (Pub. No. US20190115312A1) and Kasai et al. (US Patent No. 8,446,008).
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/E.A.T./ Examiner, Art Unit 2897
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