DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-15 in the reply filed on 02/13/2026 is acknowledged.
Claims 16-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group II invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 02/13/2026.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 6-12, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0355582 to Miyakoshi in view of Niimura et al. (US 2017/0229356, hereinafter Niimura).
With respect to claim 1, Miyakoshi teaches forming a production method (Miyakoshi, Figs. 2A-2C, 3, 4A-4C, 5A-5C, 6A-6C, 7, 8A, 9A-9C, 10A-10C, 11A-11C, 15A-15B, ¶0002, ¶0009-¶0018, ¶0041-¶0093, ¶0111-¶0112), comprising:
providing field-effect transistors (e.g., planar-type or trench-gate-type MOSFET) (Miyakoshi, Figs. 2A-2C, 4A-4C, 5A-5C, 11A-11C, ¶0041-¶0046, ¶0056-¶0066, ¶0070, ¶0074-¶0054, ¶0090) comprising sources (e.g., source regions 120 connected to the source electrode 128’ after surface metal dividing step and cutting the substrate into chips) (Miyakoshi, Figs. 2A-2C, 11A-11C, ¶0045, ¶0075), drains (e.g., drain region 112 connected to the drain electrode 130) (Miyakoshi, Figs. 2A-2C, 11A-11C, ¶0045, ¶0074), and gates (124) (Miyakoshi, Figs. 2A-2C, 11A-11C, ¶0048, ¶0057, ¶0060);
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irradiating (e.g., electron beam irradiating step, wherein the electron beam is irradiated from a first main surface in Figs. 6B-6C or from a second main surface in Figs. 15A-15B, see the annotated Fig. 6B below) (Miyakoshi, Figs. 3, 6B-6C, 8A, 15A-15B, ¶0068-¶0069, ¶0077-¶0081, ¶0111-¶0112) the field-effect transistors;
applying a voltage to the gates and the sources (e.g., a potential to the source electrode and a potential of the gate electrode are set to a ground potential) (Miyakoshi, Figs. 3, 6B-6C, 8A, 15A-15B, ¶0068-¶0069, ¶0768-¶0080),
wherein the voltage is a grounding voltage,
wherein the grounding voltage is 0 volts (V) relative to a ground voltage.
Further, Miyakoshi does not specifically disclose applying a current to the drains for a duration.
However, Niimura teaches an assessment method of measuring (Niimura, Figs. 2, 5, 8-20, ¶0010-¶0012, ¶0036-¶0053, ¶0077-¶0085) performance characteristics of a plurality of semiconductor elements wherein a state of a semiconductor element is changed by applying drain current to the semiconductor element to calculate the performance characteristics (such as avalanche breakdown voltage) (Niimura, Figs. 2, 5, 8-20, ¶0036, ¶0078, ¶0080-¶0081) of the plurality of semiconductor elements in different states. Specifically, the avalanche breakdown voltage is a drain-source voltage measured by applying a predetermined drain current to the semiconductor element during specific period of time wherein the gate and the source are short-circuited.
Thus, a person of ordinary skill in the art would recognize that applying a current to the drains for a specific period of time before irradiation step, during irradiation step, and after irradiation step, would allow to measure the performance characteristics (such as avalanche breakdown voltage) of the semiconductor element in different states.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Miyakoshi by applying a predetermined drain current to the semiconductor element during specific period of time wherein the gate and the source are short-circuited as taught by Niimura to have the production method, comprising: applying a current to the drains for a duration, in order to provide improved assessment method of measuring performance characteristics of the semiconductor elements in different states to identify the conforming products and defective products (Niimura, ¶0010-¶0012, ¶0036, ¶0080-¶0081).
Regarding claims 2 and 3, Miyakoshi in view of Niimura discloses the production method of claim 1. Further, Miyakoshi does not specifically disclose the method, wherein the current is in a range of 0.1 microamperes (μA) to 100 milliamperes (mA) (as claimed in claim 2); wherein the duration is in a range of 1 microsecond (μs) to 100 seconds (s) (as claimed in claim 3).
However, Niimura teaches applying drain current to the semiconductor element to calculate the performance characteristics (such as avalanche breakdown voltage) (Niimura, Figs. 2, 5, 8-20, ¶0036, ¶0078, ¶0080-¶0081) of the plurality of semiconductor elements in different states, wherein the drain current (id) is about 250 microamperes (μA) for a period of time (T1) of about 2 milliseconds (ms).
The current and duration are in the claimed ranges. Note that a specific example in the prior art which is within a claimed range anticipates the range (M.P.E.P. §2131.03).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Miyakoshi/Niimura by applying a predetermined drain current during specific period of time as taught by Niimura to have the production method, wherein the current is in a range of 0.1 microamperes (μA) to 100 milliamperes (mA) (as claimed in claim 2); wherein the duration is in a range of 1 microsecond (μs) to 100 seconds (s) (as claimed in claim 3), in order to provide improved assessment method of measuring performance characteristics of the semiconductor elements in different states to identify the conforming products and defective products (Niimura, ¶0010-¶0012, ¶0036, ¶0080-¶0081).
Regarding claim 6, Miyakoshi in view of Niimura discloses the production method of claim 1. Further, Miyakoshi discloses the production method, wherein providing the field-effect transistors comprises: forming the gates (124) (Miyakoshi, Figs. 2A-2C, 11A-11C, ¶0048, ¶0057, ¶0060) and the sources (e.g., source regions 120 connected to the source electrode 128’ after surface metal dividing step and cutting the substrate into chips) (Miyakoshi, Figs. 2A-2C, 11A-11C, ¶0045, ¶0075) on a first surface of a first side (e.g., a first main surface side) of a semiconductor substrate (110); and forming the drains (e.g., drain region 112 connected to the drain electrode 130, before or after forming irradiation step) (Miyakoshi, Figs. 2A-2C, 11A-11C, ¶0045, ¶0074, ¶0112) on a second surface of a second side (e.g., a second main surface side) of the semiconductor substrate (110).
Regarding claim 7, Miyakoshi in view of Niimura discloses the production method of claim 6. Further, Miyakoshi discloses the production method, wherein irradiating the field-effect transistors (Miyakoshi, Figs. 3, 6B-6C, 8A, 15A-15B, ¶0068-¶0069, ¶0077-¶0081, ¶0111-¶0112) comprises irradiating the semiconductor substrate (e.g., forming lattice defects in the semiconductor substrate 110).
Regarding claim 8, Miyakoshi in view of Niimura discloses the production method of claim 6. Further, Miyakoshi discloses the production method, further comprising: during a first test phase (e.g., Test 1) (Miyakoshi, Figs. 3, 6B-6C, 8A, 15A-15B, ¶0094-¶0100): detecting, after irradiating the field-effect transistors (e.g., 140 pieces of the semiconductor devices were prepared by a method comprising irradiating the field-effect transistors by electron beam irradiation step) (Miyakoshi, Fig. 3, ¶0095), first static parameters (e.g., threshold voltages when drain current Id was 3mA and 10 mA) of the field-effect transistors; comparing the first static parameters (e.g., threshold voltages at predetermined drain current Id) with first preset standard parameters (e.g., threshold voltages of the comparison examples 2 when the irradiation step was not performed) (Miyakoshi, Figs. 3, 12, ¶0097, ¶0100) to obtain a plurality of first tested field-effect transistors; identifying, from the field-effect transistors, the first tested field-effect transistors after the first test phase ends to obtain a plurality of second field-effect transistors (e.g., transistors having threshold voltage characteristics substantially equal to a threshold voltage characteristics in a case where the electron beam irradiation step was not performed); during a second test phase (e.g., Test 2) (Miyakoshi, Figs. 3, 13, ¶0101, ¶0101-¶0107) that follows the first test phase: detecting second static parameters (e.g., irregularities in the threshold voltage characteristics) of the second field-effect transistors; and comparing the second static parameters with second preset standard parameters to obtain a plurality of second tested field-effect transistors (e.g., the transistor wherein irregularities in the threshold voltage characteristics are not generated); and applying, during the first test phase, the current to drains (Id 3mA and 10 mA) of the first tested field-effect transistors, but does not specifically disclose applying the current to drains for the duration.
However, Niimura teaches an assessment method of measuring performance characteristics of a plurality of semiconductor elements by applying a predetermined drain current to the semiconductor element during specific period of time wherein the gate and the source are short-circuited (Niimura, Figs. 2, 5, 8-20, ¶0036, ¶0078, ¶0080-¶0081).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Miyakoshi/Niimura by applying a predetermined drain current to the semiconductor element during specific period of time as taught by Niimura to have the production method, further comprising: applying the current to drains for the duration, in order to provide improved assessment method of measuring performance characteristics of the semiconductor elements in different states to identify the conforming products and defective products (Niimura, ¶0010-¶0012, ¶0036, ¶0080-¶0081).
Regarding claim 9, Miyakoshi in view of Niimura discloses the production method of claim 6. Further, Miyakoshi discloses the production method, further comprising annealing the field-effect transistors (Miyakoshi, Figs. 3, 6B-6C, 15A-15B, ¶0071-¶0072) after irradiating the field-effect transistors.
With respect to claim 10, Miyakoshi teaches a field-effect transistor (see the annotated Figs. 2B and 6B below) (Miyakoshi, Figs. 2A-2C, 3, 4A-4C, 5A-5C, 6A-6C, 7, 8A, 9A-9C, 10A-10C, 11A-11C, 15A-15B, ¶0002, ¶0009-¶0018, ¶0041-¶0093, ¶0111-¶0112) prepared by a process comprising the steps of:
providing field-effect transistors (e.g., planar-type or trench-gate-type MOSFET) (Miyakoshi, Figs. 2A-2C, 4A-4C, 5A-5C, 11A-11C, ¶0041-¶0046, ¶0056-¶0066, ¶0070, ¶0074-¶0054, ¶0090) comprising sources (e.g., source regions 120 connected to the source electrode 128’ after surface metal dividing step and cutting the substrate into chips) (Miyakoshi, Figs. 2A-2C, 11A-11C, ¶0045, ¶0075), drains (e.g., drain region 112 connected to the drain electrode 130) (Miyakoshi, Figs. 2A-2C, 11A-11C, ¶0045, ¶0074), and gates (124)
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(Miyakoshi, Figs. 2A-2C, 11A-11C, ¶0048, ¶0057, ¶0060);
irradiating (e.g., electron beam irradiating step, wherein the electron beam is irradiated from a first main surface in Figs. 6B-6C or from a second main surface in Figs. 15A-15B) (Miyakoshi, Figs. 3, 6B-6C, 8A, 15A-15B, ¶0068-¶0069, ¶0077-¶0081, ¶0111-¶0112) the field-effect transistors;
applying a voltage to the gates and the sources (e.g., a potential to the source electrode and a potential of the gate electrode are set to a ground potential) (Miyakoshi, Figs. 3, 6B-6C, 8A, 15A-15B, ¶0068-¶0069, ¶0768-¶0080),
wherein the voltage is a grounding voltage,
wherein the grounding voltage is 0 volts (V) relative to a ground voltage.
Further, Miyakoshi does not specifically disclose applying a current to the drains for a duration.
However, Niimura teaches an assessment method of measuring (Niimura, Figs. 2, 5, 8-20, ¶0010-¶0012, ¶0036-¶0053, ¶0077-¶0085) performance characteristics of a plurality of semiconductor elements wherein a state of a semiconductor element is changed by applying drain current to the semiconductor element to calculate the performance characteristics (such as avalanche breakdown voltage) (Niimura, Figs. 2, 5, 8-20, ¶0036, ¶0078, ¶0080-¶0081) of the plurality of semiconductor elements in different states. Specifically, the avalanche breakdown voltage is a drain-source voltage measured by applying a predetermined drain current to the semiconductor element during specific period of time wherein the gate and the source are short-circuited.
Thus, a person of ordinary skill in the art would recognize that applying a current to the drains for a specific period of time before irradiation step, during irradiation step, and after irradiation step, would allow to measure the performance characteristics (such as avalanche breakdown voltage) of the semiconductor element in different states.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the process for preparing the field-effect transistor of Miyakoshi by applying a predetermined drain current to the semiconductor element during specific period of time wherein the gate and the source are short-circuited as taught by Niimura to have the field-effect transistor prepared by a process comprising the step of: applying a current to the drains for a duration, in order to provide improved semiconductor element prepared by the assessment method including measuring performance characteristics of the semiconductor elements in different states to identify the conforming products and defective products (Niimura, ¶0010-¶0012, ¶0036, ¶0080-¶0081).
Regarding claims 11 and 12, Miyakoshi in view of Niimura discloses the field-effect transistor of claim 10. Further, Miyakoshi does not specifically disclose the field-effect transistor, wherein the current is in a range of 0.1 microamperes (μA) to 100 milliamperes (mA) (as claimed in claim 11); wherein the duration is in a range of 1 microsecond (μs) to 100 seconds (s) (as claimed in claim 12).
However, Niimura teaches applying drain current to the semiconductor element to calculate the performance characteristics (such as avalanche breakdown voltage) (Niimura, Figs. 2, 5, 8-20, ¶0036, ¶0078, ¶0080-¶0081) of the plurality of semiconductor elements in different states, wherein the drain current (id) is about 250 microamperes (μA) for a period of time (T1) of about 2 milliseconds (ms).
The current and duration are in the claimed ranges. Note that a specific example in the prior art which is within a claimed range anticipates the range (M.P.E.P. §2131.03).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the process for preparing the field-effect transistor of Miyakoshi/Niimura by applying a predetermined drain current during specific period of time as taught by Niimura to have the field-effect transistor prepared by a process, wherein the current is in a range of 0.1 microamperes (μA) to 100 milliamperes (mA) (as claimed in claim 11); wherein the duration is in a range of 1 microsecond (μs) to 100 seconds (s) (as claimed in claim 12), in order to provide improved assessment method of measuring performance characteristics of the semiconductor elements in different states to identify the conforming products and defective products (Niimura, ¶0010-¶0012, ¶0036, ¶0080-¶0081).
Regarding claim 15, Miyakoshi in view of Niimura discloses the field-effect transistor of claim 10. Further, Miyakoshi discloses the field-effect transistor, wherein the gate (124) (Miyakoshi, Figs. 2A-2C, 11A-11C, ¶0048, ¶0057, ¶0060) and the source (e.g., source regions 120 connected to the source electrode 128’ after surface metal dividing step and cutting the substrate into chips) (Miyakoshi, Figs. 2A-2C, 11A-11C, ¶0045, ¶0075) are formed on a first surface of a first side (e.g., a first main surface side) of a semiconductor substrate (110); and the drain (e.g., drain region 112 connected to the drain electrode 130, before or after forming irradiation step) (Miyakoshi, Figs. 2A-2C, 11A-11C, ¶0045, ¶0074, ¶0112) is formed on a second surface of a second side (e.g., a second main surface side) of the semiconductor substrate (110).
Claims 4-5 and 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0355582 to Miyakoshi in view of Niimura (US 2017/0229356) as applied to claim 1, and further in view of Bobde et al. (US 2015/0021682, hereinafter Bobde).
Regarding claims 4 and 5, Miyakoshi in view of Niimura discloses the production method of claim 1. Further, Miyakoshi does not specifically disclose the production method, wherein the reverse voltage is a positive voltage when the field-effect transistors are P-type transistors (as claimed in claim 4); wherein the reverse voltage is a negative voltage when the field-effect transistors are N-type transistors (as claimed in claim 5).
However, Bobde teaches forming a normally on high voltage switch device (Bobde, Figs. 5-7, ¶0016-¶0017, ¶0026-¶0036) formed by using high-voltage trench MOSFET fabrication process for AC-to-DC power converter applications, wherein the trench gate electrode (152) is shorted to the source electrode (166), and by applying the reverse bias voltage to the gate region relative to the source region to switch off the electric current of the FET device, wherein the reverse voltage is a positive gate-source voltage when the field-effect transistors are P-type transistors, and wherein the reverse voltage is a negative gate-source voltage when the field-effect transistors are N-type transistors.
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Miyakoshi/Niimura by forming normally on high voltage switch device using high-voltage trench MOSFET fabrication process as taught by Bobde to have the production method, wherein the reverse voltage is a positive voltage when the field-effect transistors are P-type transistors (as claimed in claim 4); wherein the reverse voltage is a negative voltage when the field-effect transistors are N-type transistors (as claimed in claim 5), in order to provide improved high-voltage trench MOSFET for AC-to-DC power converter applications (Bobde, ¶0016-¶0017, ¶0034-¶0036).
Regarding claims 13 and 14, Miyakoshi in view of Niimura discloses the field-effect transistor of claim 10. Further, Miyakoshi does not specifically disclose the field-effect transistor, wherein the reverse voltage is a positive voltage when the field-effect transistor is P-type transistors (as claimed in claim 13); wherein the reverse voltage is a negative voltage when the field-effect transistor is N-type transistors (as claimed in claim 14).
However, Bobde teaches forming a normally on high voltage switch device (Bobde, Figs. 5-7, ¶0016-¶0017, ¶0026-¶0036) formed by using high-voltage trench MOSFET fabrication process for AC-to-DC power converter applications, wherein the trench gate electrode (152) is shorted to the source electrode (166), and by applying the reverse bias voltage to the gate region relative to the source region to switch off the electric current of the FET device, wherein the reverse voltage is a positive gate-source voltage when the field-effect transistors are P-type transistors, and wherein the reverse voltage is a negative gate-source voltage when the field-effect transistors are N-type transistors.
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the field-effect transistor of Miyakoshi/Niimura by forming normally on high voltage switch device using high-voltage trench MOSFET fabrication process as taught by Bobde to have the field-effect transistor, wherein the reverse voltage is a positive voltage when the field-effect transistor is P-type transistors (as claimed in claim 13); wherein the reverse voltage is a negative voltage when the field-effect transistor is N-type transistors (as claimed in claim 14), in order to provide improved high-voltage trench MOSFET for AC-to-DC power converter applications (Bobde, ¶0016-¶0017, ¶0034-¶0036).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATALIA GONDARENKO whose telephone number is (571)272-2284. The examiner can normally be reached 9:30 AM-7:30 PM.
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/NATALIA A GONDARENKO/Primary Examiner, Art Unit 2891