DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to the amendments filed on 05/12/2026.
Applicant’s amendments filed 05/12/2026 have been fully considered and reviewed by the examiner. The examiner notes the amendment of claims 1, 4, 6, 10, 13, and 15; the cancellation of claims 5, 8, 14, and 16-20; and the addition of new claims 21-28.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 10-12, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0355582 to Miyakoshi in view of Charbuillet et al. (US Patent No. 9,000,785, hereinafter Charbuillet) and Niimura et al. (US 2017/0229356, hereinafter Niimura).
With respect to claim 10, Miyakoshi teaches a field-effect transistor (see the annotated Figs. 2B and 6B below) (Miyakoshi, Figs. 2A-2C, 3, 4A-4C, 5A-5C, 6A-6C, 7, 8A, 9A-9C, 10A-10C, 11A-11C, 15A-15B, ¶0002, ¶0009-¶0018, ¶0041-¶0093, ¶0111-¶0112) prepared by a process comprising the steps of:
providing field-effect transistors (e.g., planar-type or trench-gate-type MOSFET) (Miyakoshi, Figs. 2A-2C, 4A-4C, 5A-5C, 11A-11C, ¶0041-¶0046, ¶0056-¶0066, ¶0070, ¶0074-¶0054, ¶0090) comprising sources (e.g., source regions 120 connected to the source electrode 128’ after surface metal dividing step and cutting the substrate into chips) (Miyakoshi, Figs. 2A-2C, 11A-11C, ¶0045, ¶0075), drains (e.g., drain region 112 connected to the drain electrode 130) (Miyakoshi, Figs. 2A-2C, 11A-11C, ¶0045, ¶0074), and gates (124) (Miyakoshi, Figs. 2A-2C, 11A-11C, ¶0048, ¶0057, ¶0060);
irradiating (e.g., electron beam irradiating step, wherein the electron beam is irradiated from a first main surface in Figs. 6B-6C or from a second main surface in Figs. 15A-15B) (Miyakoshi, Figs. 3, 6B-6C, 8A, 15A-15B, ¶0068-¶0069, ¶0077-¶0081, ¶0111-¶0112) the field-effect transistors;
applying a voltage to the gates and the sources (e.g., a potential to the source electrode and a potential of the gate electrode are set to a ground potential) (Miyakoshi, Figs. 3, 6B-6C, 8A, 15A-15B, ¶0068-¶0069, ¶0768-¶0080),
wherein the voltage is a grounding voltage that is 0 volts (V) relative to a ground voltage.
Further, Miyakoshi does not specifically disclose (1) the field-effect transistors share a semiconductor substrate; (2) applying a current to the drains for a duration.
Regarding (1), Charbuillet teaches a plurality of field effect transistors (Charbuillet, Figs. 3, 7-8, Col. 1, lines 5-6, lines 10-30; Col. 2, lines 25-40; Col. 3, lines 23-47; Col. 4, lines 37-46; Col. 5, lines 34-41) on the same substrate (wafer) for a testing the properties of the transistors, to provide the field-effect transistors having faster operation, smaller transistor size, and less power consumption.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify a field-effect transistor of Miyakoshi by forming a plurality of field-effect transistors on the same wafer as taught by Charbuillet to have the field-effect transistor, wherein the field-effect transistors share a semiconductor substrate, in order to to provide the field-effect transistors having faster operation, smaller transistor size, and less power consumption (Charbuillet, Col. 1, lines 5-6, lines 10-30; Col. 2, lines 25-40; Col. 4, lines 37-46; Col. 5, lines 34-41).
Regarding (2), Niimura teaches an assessment method of measuring (Niimura, Figs. 2, 5, 8-20, ¶0010-¶0012, ¶0036-¶0053, ¶0077-¶0085) performance characteristics of a plurality of semiconductor elements wherein a state of a semiconductor element is changed by applying drain current to the semiconductor element to calculate the performance characteristics (such as avalanche breakdown voltage) (Niimura, Figs. 2, 5, 8-20, ¶0036, ¶0078, ¶0080-¶0081) of the plurality of semiconductor elements in different states. Specifically, the avalanche breakdown voltage is a drain-source voltage measured by applying a predetermined drain current to the semiconductor element during specific period of time wherein the gate and the source are short-circuited.
Thus, a person of ordinary skill in the art would recognize that applying a current to the drains for a specific period of time before irradiation step, during irradiation step, and after irradiation step, would allow to measure the performance characteristics (such as avalanche breakdown voltage) of the semiconductor element in different states.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify a field-effect transistor of Miyakoshi by applying a predetermined drain current to the semiconductor element during specific period of time wherein the gate and the source are short-circuited as taught by Niimura to have the field-effect transistor comprising: applying a current to the drains for a duration, in order to provide improved semiconductor element prepared by the assessment method including measuring performance characteristics of the semiconductor elements in different states to identify the conforming products and defective products (Niimura, ¶0010-¶0012, ¶0036, ¶0080-¶0081).
Further, the limitations “detecting, during a first test phase and after irradiating the field-effect transistors, first static parameters of the field-effect transistors;
comparing, during the first test phase and while applying the current to the drains, first static parameters with first preset standard parameters to obtain a plurality of first tested field- effect transistors;
identifying, from the field-effect transistors, the first tested field-effect transistors after the first test phase ends to obtain a plurality of second field-effect transistors;
detecting, during a second test phase and following the first test phase, second static parameters of the second field-effect transistors: and comparing, during the second test phase and while applying the current to the drains of the second field-effect transistors, second static parameters with second preset standard parameters to obtain a plurality of second tested field-effect transistors” are directed towards the process of making a field-effect transistor comprising the field-effect transistors that share a semiconductor substrate and are irradiated, and capable of performing by applying a voltage to the gates and the sources, and a current to the drains for a duration.
It is well settled that "product-by-process" limitations in claims drawn to structure are directed to the product, per se, no matter how actually made. “[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985), which make it clear that it is the patentability of the final product per se which must be determined in a "product by process" claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in "product by process" claims or otherwise. The above case law further makes clear that applicant has the burden of showing that the method language necessarily produces a structural difference. As such, the language “detecting, during a first test phase and after irradiating the field-effect transistors, first static parameters of the field-effect transistors;
comparing, during the first test phase and while applying the current to the drains, first static parameters with first preset standard parameters to obtain a plurality of first tested field- effect transistors;
identifying, from the field-effect transistors, the first tested field-effect transistors after the first test phase ends to obtain a plurality of second field-effect transistors;
detecting, during a second test phase and following the first test phase, second static parameters of the second field-effect transistors: and comparing, during the second test phase and while applying the current to the drains of the second field-effect transistors, second static parameters with second preset standard parameters to obtain a plurality of second tested field-effect transistors” only requires a structure, a field-effect transistor comprising the field-effect transistors that share a semiconductor substrate and are irradiated, and capable of performing by applying a voltage to the gates and the sources, and a current to the drains for a duration, which does not distinguish the invention from the combination Miyakoshi/Charbuillet/Niimura that teaches the structure as claimed.
Regarding claims 11 and 12, Miyakoshi in view of Charbuillet and Niimura discloses the field-effect transistor of claim 10. Further, Miyakoshi does not specifically disclose the field-effect transistor, wherein the current is in a range of 0.1 microamperes (μA) to 100 milliamperes (mA) (as claimed in claim 11); wherein the duration is in a range of 1 microsecond (μs) to 100 seconds (s) (as claimed in claim 12).
However, Niimura teaches applying drain current to the semiconductor element to calculate the performance characteristics (such as avalanche breakdown voltage) (Niimura, Figs. 2, 5, 8-20, ¶0036, ¶0078, ¶0080-¶0081) of the plurality of semiconductor elements in different states, wherein the drain current (id) is about 250 microamperes (μA) for a period of time (T1) of about 2 milliseconds (ms).
The current and duration are in the claimed ranges. Note that a specific example in the prior art which is within a claimed range anticipates the range (M.P.E.P. §2131.03).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the the field-effect transistor of Miyakoshi/ Charbuillet/Niimura by applying a predetermined drain current during specific period of time as taught by Niimura to have the field-effect transistor prepared by a process, wherein the current is in a range of 0.1 microamperes (μA) to 100 milliamperes (mA) (as claimed in claim 11); wherein the duration is in a range of 1 microsecond (μs) to 100 seconds (s) (as claimed in claim 12), in order to provide improved assessment method of measuring performance characteristics of the semiconductor elements in different states to identify the conforming products and defective products (Niimura, ¶0010-¶0012, ¶0036, ¶0080-¶0081).
Regarding claim 13, Miyakoshi in view of Charbuillet and Niimura discloses the field-effect transistor of claim 10. Further, Miyakoshi discloses the field-effect transistor, wherein the first parameters are one (e.g., a threshold voltage) (Miyakoshi, ¶0009) or more of a threshold voltage, a drain leakage current, uniformity of leakage current, or a drain-source withstanding voltage.
Regarding limitation “the first static parameters”, it is noted that the language, term, or phrase "the static parameters" is directed towards the process of making the field-effect transistor. It is well settled that "product-by-process" limitations in claims drawn to structure are directed to the product, per se, no matter how actually made. “[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985), which make it clear that it is the patentability of the final product per se which must be determined in a "product by process" claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in "product by process" claims or otherwise. The above case law further makes clear that applicant has the burden of showing that the method language necessarily produces a structural difference. As such, the language “the first static parameters” only requires a structure, the field-effect transistor having parameter (e.g., threshold voltage), which does not distinguish the invention from Miyakoshi who teaches the structure as claimed.
Regarding claim 15, Miyakoshi in view of Charbuillet and Niimura discloses the field-effect transistor of claim 10. Further, Miyakoshi discloses the field-effect transistor, wherein the gates (124) (Miyakoshi, Figs. 2A-2C, 11A-11C, ¶0048, ¶0057, ¶0060) and the sources (e.g., source regions 120 connected to the source electrode 128’ after surface metal dividing step and cutting the substrate into chips) (Miyakoshi, Figs. 2A-2C, 11A-11C, ¶0045, ¶0075) are formed on a first surface of a first side (e.g., a first main surface side) of the semiconductor substrate (110); and the drains (e.g., drain region 112 connected to the drain electrode 130, before or after forming irradiation step) (Miyakoshi, Figs. 2A-2C, 11A-11C, ¶0045, ¶0074, ¶0112) is formed on a second surface of a second side (e.g., a second main surface side) of the semiconductor substrate (110).
Allowable Subject Matter
Claims 1-4, 6-7, 9, and 21-28 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
The search of the prior art does not disclose or reasonably suggest a production method comprising irradiating the field-effect transistors, detecting first static parameters of the field-effect transistors during a first test phase and obtaining a plurality of first tested field- effect transistors, detecting second static parameters of the second field-effect transistors during a second test phase and obtaining a plurality of second tested field- effect transistors, in combinations with other claim limitations as required by claims 1 and 21.
Response to Arguments
Applicant's arguments filed 05/12/2026 have been fully considered but they are not persuasive.
In response to Applicant's arguments that "Independent claims 1 and 10 have been amended to include limitations similar to those previously recited in dependent claim 8, among other limitations”, the examiner submits that limitations of the previously submitted claim 8 are drawn to the production method. It is well settled that "product-by-process" limitations in claims drawn to structure are directed to the product, per se, no matter how actually made. “[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985), which make it clear that it is the patentability of the final product per se which must be determined in a "product by process" claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in "product by process" claims or otherwise. The above case law further makes clear that applicant has the burden of showing that the method language necessarily produces a structural difference. As such, the language “detecting, during a first test phase and after irradiating the field-effect transistors, first static parameters of the field-effect transistors;
comparing, during the first test phase and while applying the current to the drains, first static parameters with first preset standard parameters to obtain a plurality of first tested field- effect transistors;
identifying, from the field-effect transistors, the first tested field-effect transistors after the first test phase ends to obtain a plurality of second field-effect transistors;
detecting, during a second test phase and following the first test phase, second static parameters of the second field-effect transistors: and comparing, during the second test phase and while applying the current to the drains of the second field-effect transistors, second static parameters with second preset standard parameters to obtain a plurality of second tested field-effect transistors” only requires a structure, a field-effect transistor comprising the field-effect transistors that share a semiconductor substrate and are irradiated, and capable of performing by applying a voltage to the gates and the sources, and a current to the drains for a duration, which does not distinguish the invention from the combination Miyakoshi/Charbuillet/Niimura that teaches the structure as claimed.
Thus, the above applicant’s argument is not persuasive, and the rejection of claim 10 under 35 USC over Miyakoshi in view of Charbuillet and Niimura is maintained.
Regarding dependent claims 11-13 and 15 which depend on the independent claim 10, the examiner respectfully submits that the applicant’s arguments with respect to dependent claims are not persuasive for the above reasons, thus, the rejections of the dependent claims are sustained.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATALIA GONDARENKO whose telephone number is (571)272-2284. The examiner can normally be reached 9:30 AM-7:30 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at 571-272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/NATALIA A GONDARENKO/Primary Examiner, Art Unit 2891
Prosecution Insights