DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 6, 9-11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sasao et al. (US 2021/0345496 A1 hereinafter referred to as “Sasao”).
With respect to claim 1, Sasao discloses, in Figs.1-25, a semiconductor circuit comprising: an input capacitor (Ci) having a first electrode and a second electrode (see Par.[0066]-[0067] wherein the input line 202 is connected to the input capacitor Ci used to stabilize the input voltage V.sub.IN. The output line 204 is connected to the output capacitor Co used to smooth the output voltage V.sub.OUT); a first arm (220_1) circuit including a first switching element (M1_1) and a second switching element (M2_1) that are connected in series with each other, wherein the first switching element (M1_1) is electrically connected to the first electrode, and the second switching element (M2_1) is electrically connected to the second electrode; a second arm circuit (220_N) including a third switching element (M1_N) and a fourth switching element (M2_N) that are connected in series with each other, wherein the third switching element (M1_N) is electrically connected to the first electrode, and the fourth switching element (M2_N) is electrically connected to the second electrode (see Par.[0068], [0074], [0078] wherein the power modules 220 include a high-side switch (switching transistor) M1, a low-side switch (synchronous rectifier transistor transistor) M2, a high-side driver 222, a low-side driver 224, and a logic circuit 226; the case of an application that causes the plurality of power modules 220_1 to 220_N to generate a large amount of heat, it is necessary to use a heat sink to cool the plurality of power modules 220_1 to 220_N); and a shield (240) that overlaps with at least a part of the second arm circuit (220_N) in a plan view and is externally grounded, wherein the first arm circuit (220_1) has a first path from a first node (220_1) having a same potential as the first electrode to a second node (202_N) having a same potential as the second electrode (see Par.[0067]-[0068] wherein the DC/DC converter 200 receives an input voltage V.sub.IN of the input line 202, generates an output voltage V.sub.OUT stabilized at a predetermined level, and supplies the generated output voltage V.sub.OUT to the load; the high-side switch M1 is disposed between the VIN pin and the SW pin; the low-side switch M2 is disposed between the SW pin and the PGND pin; see Par.[0106] wherein the heat sink 240B in FIGS. 16(a) and 16(b) is excellent in electromagnetic noise shielding performance and able to improve EMC (Electro Magnetic Compatibility)), wherein the second arm circuit (220_N) has a second path from the first node (220_1) to the second node (220_N), wherein a length of the second path is longer than a length of the first path (see Fig.21 wherein ), and wherein a length of a section of the shield (240) that overlaps with the second arm circuit in a plan view and extends along the second path is longer than a length of a section of the shield that overlaps with the first arm circuit in a plan view and extends along the first path (see Fig.15, wherein shield 240B completely covered power module 220; as such, given that second path is longer than the first path a length of a section of the shield (240) that overlaps with the second arm circuit in a plan view and extends along the second path is longer than a length of a section of the shield that overlaps with the first arm circuit in a plan view and extends along the first path).
With respect to claim 2, Sasao discloses, in Figs.1-25, the semiconductor circuit, wherein the shield (240) overlaps with an entirety of the second arm circuit in a plan view (see Fig.15, wherein shield 240B completely covered power module 220; as such, given that second path is longer than the first path a length of a section of the shield (240) that overlaps with the second arm circuit in a plan view and extends along the second path is longer than a length of a section of the shield that overlaps with the first arm circuit in a plan view and extends along the first path).
With respect to claim 3, Sasao discloses, in Figs.1-25, the semiconductor circuit, wherein the first arm circuit further includes a first wiring (202-1) that electrically connects the first node (Vin) and the first switching element (M1), and a second wiring (202-1) that electrically connects the second node and the second switching element (M2), wherein the second arm circuit further includes a third wiring (204) that electrically connects the first node and the third switching element (M1), and a fourth wiring that electrically connects the second node and the fourth switching element (M2), and wherein the shield (240) overlaps with at least the third wiring and the fourth wiring in a plan view.
With respect to claim 6, Sasao discloses, in Figs.1-25, the semiconductor circuit, wherein the shield overlaps with each of the input capacitor, the first wiring, the second wiring, the third wiring, and the fourth wiring in a plan view.
With respect to claim 9, Sasao discloses, in Figs.1-25, a semiconductor device comprising: a semiconductor circuit; and a base material (300) on which the semiconductor circuit is mounted (see Par.[0094] wherein it is assumed that at least one of the N power modules 220 is mounted on a sub-mounting surface SB of the printed circuit board 300).
With respect to claim 10, Sasao discloses, in Figs.1-25, the semiconductor device, wherein a part of each of the first arm circuit and the second arm circuit is accommodated in the base material, and wherein the input capacitor is conductively bonded to the base material.
With respect to claim 11, Sasao discloses, in Figs.1-25, the semiconductor device, further comprising a semiconductor element including the first switching element, the second switching element, the third switching element, and the fourth switching element, wherein the semiconductor element is conductively bonded to the base material.
Claims 1-7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tago et al. (US 2013/0264872 A1 hereinafter referred to as “Tago”).
With respect to claim 1, Tago discloses, in Figs.1-7, a semiconductor circuit comprising: an input capacitor (213, 24) having a first electrode and a second electrode (see Par.[0026] wherein capacitors 23 and 24 including upper and lower electrodes are disclosed); a first arm circuit (31) including a first switching element (311) and a second switching element (311) that are connected in series with each other, wherein the first switching element (311) is electrically connected to the first electrode, and the second switching element (311) is electrically connected to the second electrode (see Par.[0026]-[0027] wherein the power conversion circuit 31 includes a plurality of switching elements 311; according to the first embodiment, the switching element 311 is a semiconductor device capable of switching such as IGBT (insulated gate bipolar transistor) and configured by six switching elements; three switching elements among the six switching elements 311 are connected to the upper main line 2 which is connected to the output side of the filter circuit 20 so as to constitute an upper arm); a second arm circuit (32) including a third switching element (321) and a fourth switching element (321) that are connected in series with each other, wherein the third switching element is electrically connected to the first electrode, and the fourth switching element is electrically connected to the second electrode (see Par.[0028] wherein the power conversion circuit 32 converts the power transmitted from the battery 10 via the filter circuit 20 such that the control circuit 72 (described later) controls the switching element 321 to be ON and OFF so as to convert the power, and outputs the converted power to the motor 12); and a shield (51, 61-62) that overlaps with at least a part of the second arm circuit (32) in a plan view and is externally grounded (80) (see Par.[0042] wherein the first casing 51 and the second casings 61, 62 and 63 are made of metal such as aluminum that is capable of shielding electromagnetic waves so that electromagnetic waves entering to the filter circuit 20 and power conversion circuits 31, 32 and 33 from outside the casing can be suppressed; see Par.[0035] wherein the ECU 80 operates with a power supplied by the other low voltage power source includes ground bench power supplies), wherein the first arm circuit has a first path from a first node/(upper main line 2 node) having a same potential as the first electrode to a second node/(lower main line 3 node) having a same potential as the second electrode, wherein the second arm circuit has a second path from the first node to the second node, wherein a length of the second path is longer than a length of the first path, and wherein a length of a section of the shield that overlaps with the second arm circuit in a plan view and extends along the second path is longer than a length of a section of the shield that overlaps with the first arm circuit in a plan view and extends along the first path (see Par.[0026] wherein he coil 21 is disposed at an upper main line 2 connected to the positive terminal of the battery 10; the coil 22 is disposed at a lower main line 3 connected to the negative terminal of the battery 10; see, for example, Fig.7, wherein path between 51 and 31 is shorter than that between 51 and 32).
With respect to claim 2, Tago discloses, in Figs.1-7, the semiconductor circuit, wherein the shield (62) overlaps with an entirety of the second arm circuit in a plan view.
With respect to claim 3, Tago discloses, in Figs.1-7, the semiconductor circuit, wherein the first arm circuit further includes a first wiring that electrically connects the first node and the first switching element, and a second wiring that electrically connects the second node and the second switching element, wherein the second arm circuit further includes a third wiring that electrically connects the first node and the third switching element, and a fourth wiring that electrically connects the second node and the fourth switching element, and wherein the shield overlaps with at least the third wiring and the fourth wiring in a plan view (see Par.[0026] wherein he coil 21 is disposed at an upper main line 2 connected to the positive terminal of the battery 10; the coil 22 is disposed at a lower main line 3 connected to the negative terminal of the battery 10; see, for example, Fig.7, wherein path between 51 and 31 is shorter than that between 51 and 32).
With respect to claim 4, Tago discloses, in Figs.1-7, the semiconductor circuit, wherein the shield (51, 61, 62) includes a first shield (61) and a second shield (62) that are separated from each other, wherein the first shield overlaps with the third wiring in a plan view, and wherein the second shield overlaps with the fourth wiring in a plan view (see Par.[0042] wherein the first casing 51 and the second casings 61, 62 and 63 are made of metal such as aluminum that is capable of shielding electromagnetic waves so that electromagnetic waves entering to the filter circuit 20 and power conversion circuits 31, 32 and 33 from outside the casing can be suppressed).
With respect to claim 5, Tago discloses, in Figs.1-7, the semiconductor circuit, wherein the first shield (61) overlaps with the first wiring in a plan view, and wherein the second shield (62) overlaps with the second wiring in a plan view (see Par.[0042] wherein the first casing 51 and the second casings 61, 62 and 63 are made of metal such as aluminum that is capable of shielding electromagnetic waves so that electromagnetic waves entering to the filter circuit 20 and power conversion circuits 31, 32 and 33 from outside the casing can be suppressed).
With respect to claim 6, Tago discloses, in Figs.1-7, the semiconductor circuit, wherein the shield (51) overlaps with each of the input capacitor (23, 24), the first wiring, the second wiring, the third wiring, and the fourth wiring in a plan view.
With respect to claim 7, Tago discloses, in Figs.1-7, the semiconductor circuit, further comprising an inductor (21-22) electrically connected to the first switching element (311), the second switching element (311), the third switching element (321), and the fourth switching element (321), wherein the inductor is located outside the shield (31-32) in a plan view.
Claims 1-3, 6, 9-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Fukumasu et al. (US 2014/0240946 A1 hereinafter referred to as “Fukumasu”).
With respect to claim 1, Fukumasu discloses, in Figs.1-10, a semiconductor circuit comprising: an input capacitor (Cr/138) having a first electrode and a second electrode (see Par.[0031] wherein the LC filter circuit that is installed in order to reduce the output noise of the DC/DC converter device 100, and constitutes a .pi.-type LC filter circuit together with the smoothing capacitor 138 mounted on the substrate of the step-up circuit section 132); a first arm circuit including a first switching element (SWA1/S1) and a second switching element (SWA2/S2) that are connected in series with each other, wherein the first switching element is electrically connected to the first electrode, and the second switching element is electrically connected to the second electrode; a second arm circuit including a third switching element (SWA3) and a fourth switching element (SWA4) that are connected in series with each other, wherein the third switching element is electrically connected to the first electrode, and the fourth switching element is electrically connected to the second electrode (see Par.[0026] wherein the main transformer 133 corresponds to a transformer Tr, the inductor element 134 corresponds to the reactors L1 and L2 of the current doubler, and the switching element 136 corresponds to the switching element SWA1-SWA4 and SAWB1-SWB4, respectively); and a shield (102) that overlaps with at least a part of the second arm circuit in a plan view and is externally grounded, wherein the first arm circuit has a first path from a first node having a same potential as the first electrode to a second node having a same potential as the second electrode, wherein the second arm circuit has a second path from the first node to the second node, wherein a length of the second path is longer than a length of the first path, and wherein a length of a section of the shield that overlaps with the second arm circuit in a plan view and extends along the second path is longer than a length of a section of the shield that overlaps with the first arm circuit in a plan view and extends along the first path (see Fig.2, wherein there are longer and shorthest paths circuitry from a node to node; see Par.[0032]-[0036] wherein the shield wall 102 and the shield wall of the base plate 107 so as to intersect with each other when seen from the housing, the distance of the LC filter circuit from the step-down circuit section 131 and the step-up circuit section 132 that are noise sources can be increased, the noise to be mixed can be reduced, and the shield effect can be increased).
With respect to claim 2, Fukumasu discloses, in Figs.1-10, the semiconductor circuit, wherein the shield (102) overlaps with an entirety of the second arm circuit in a plan view.
With respect to claim 3, Fukumasu discloses, in Figs.1-10, the semiconductor circuit, wherein the first arm circuit further includes a first wiring that electrically connects the first node and the first switching element, and a second wiring that electrically connects the second node and the second switching element, wherein the second arm circuit further includes a third wiring that electrically connects the first node and the third switching element, and a fourth wiring that electrically connects the second node and the fourth switching element, and wherein the shield overlaps with at least the third wiring and the fourth wiring in a plan view.
With respect to claim 6, Fukumasu discloses, in Figs.1-10, the semiconductor circuit, wherein the shield (102) overlaps with each of the input capacitor, the first wiring, the second wiring, the third wiring, and the fourth wiring in a plan view.
With respect to claim 9, Fukumasu discloses, in Figs.1-10, a semiconductor device comprising: a semiconductor circuit; and a base material (130) on which the semiconductor circuit is mounted (see Par.[0028]-[0029] wherein the control circuit board 130 is fixed onto a metal base plate 137).
With respect to claim 10, Fukumasu discloses, in Figs.1-10, the semiconductor device, wherein a part of each of the first arm circuit and the second arm circuit is accommodated in the base material, and wherein the input capacitor is conductively bonded to the base material.
With respect to claim 11, Fukumasu discloses, in Figs.1-10, the semiconductor device, further comprising a semiconductor element including the first switching element, the second switching element, the third switching element, and the fourth switching element, wherein the semiconductor element is conductively bonded to the base material.
With respect to claim 12, Fukumasu discloses, in Figs.1-10, the semiconductor device, further comprising a sealing resin that covers at least the semiconductor element (see Par.[0034] wherein using a conductive seal material in order to fill the gap between the shield wall 102 and the case cover 111, the shield effect can be increased further).
With respect to claim 13, Fukumasu discloses, in Figs.1-10, the semiconductor device, wherein the base material has a main surface facing the semiconductor element in a first direction, and a back surface facing opposite to the main surface in the first direction, and wherein the shield is exposed to the outside from the back surface.
With respect to claim 14, Fukumasu discloses, in Figs.1-10, the semiconductor device, wherein the shield is exposed to the outside from the main surface.
With respect to claim 15, Fukumasu discloses, in Figs.1-10, the semiconductor device, wherein a part of the shield is accommodated in the sealing resin.
With respect to claim 16, Fukumasu discloses, in Figs.1-10, the semiconductor device, wherein the sealing resin covers the input capacitor.
With respect to claim 17, Fukumasu discloses, in Figs.1-10, the semiconductor device, further comprising a plurality of terminals exposed to the outside from the back surface, wherein each of the plurality of terminals is electrically connected to at least one of the input capacitor, the first arm circuit, or the second arm circuit.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Sasao in view of Kazanchian (US 2010/0060454 A1).
With respect to claim 7, Sasao discloses all the claimed limitations of claim 1. However, Sasao does not explicitly disclose all the claimed limitations of claim 7.
Kazanchian discloses, in Figs.1-14, the semiconductor circuit, further comprising an inductor (15) electrically connected to the first switching element, the second switching element, the third switching element, and the fourth switching element (see Par.[0037] wherein Pins 5-7 can be selected to perform as serial UART transceivers, receivers, three-input switch logic transmitters, or three-output switch logic receivers), wherein the inductor (15) is located outside the shield (22) in a plan view (see Par.[0033] wherein RF output network units 74, preferably in the form of inductors and/or capacitors, are located at the internal feed point 75 (shown in broken line in FIGS. 2 and 3) of the chip antenna 15 outside of the RF shield 22 to match the chip antenna to the components inside the shield).
Sasao and Kazanchian are analogous art because they are all directed to a electronic package device, and one of ordinary skill in the art would have had a reasonable expectation of success by modifying Sasao to include Kazanchian because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to modify shield structure over the circuit device by including an inductor-capacitor circuit outside shield as taught by Kazanchian in order to utilize the RF module with the shield configuration uncovering an inductor-capacitor thereby allowing the RF module to still have an effective antenna pattern without undesirable antenna feedback incident on the RF matching/filtering network.
With respect to claim 8, Kazanchian discloses, in Figs.1-14, the semiconductor circuit, further comprising an output capacitor electrically connected to the inductor, wherein the output capacitor is located outside the shield in a plan view.
Citation of Pertinent Prior Art
The prior art made of record (e.g.; see PTO-892) and not relied upon is considered pertinent to applicant's disclosure.
Examiner’s Telephone/Fax Contacts
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOULOUCOULAYE INOUSSA whose telephone number is (571)272-0596. The examiner can normally be reached Monday-Friday (10-18).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JEFF W NATALINI can be reached at 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Mouloucoulaye Inoussa/ Primary Examiner, Art Unit 2818