Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to application No. 18477907 filed on 09/29/2023.
Information Disclosure Statement
Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Election/Restrictions
Applicant’s election without traverse of claims 1-7, 9, 12-15 in the reply filed on 2/02/2026 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(B) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2, 15 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 2 recites the limitation “layer contact via structures…”. The metes and bounds of the claimed limitation can not be determined for the following reasons: This limitation has not been defined before and lacks proper antecedent basis.
Claim 15 recites the limitation “layer contact via structures…”, “first-type support pillar structures…”, “second-type support pillar structures…”. The metes and bounds of the claimed limitation can not be determined for the following reasons: These limitations have not been defined before and lack proper antecedent basis.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 9, 12, 14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wu et al. (CN 114975467 A).
Regarding independent claim 1, Wu et al. teach a three-dimensional memory device, comprising:
a pair of alternating stacks, wherein each alternating stack within the pair of alternating stacks comprises insulating layers (Fig. 2, specification discloses interlayer insulating film) and electrically conductive layers (Fig. 2, specification discloses gate layers) that are interlaced along a vertical direction, and
wherein the pair of alternating stacks are laterally spaced from each other by a lateral isolation trench (Fig. 2, element 11) that laterally extends along a first horizontal direction;
memory openings (Fig. 2, element 21) vertically extending through a respective one of the pair of alternating stacks;
memory opening fill structures located in a respective one of the memory openings and comprising a respective vertical stack of memory elements (Fig. 2, elements 22 & 24) and a respective vertical semiconductor channel (Fig. 2, element 23); and
a lateral isolation trench fill structure located in the lateral isolation trench, the lateral isolation trench fill structure comprising: a plurality of neck portions (Fig. 4, element 111a) having a pair of straight sidewalls which extend along the first horizontal direction and having a first width along a second horizontal direction that is perpendicular to the first horizontal direction; and
a plurality of laterally bulging portions (Fig. 4, element 112a) having a second width along the second horizontal direction that is greater than the first width, wherein the plurality of laterally bulging portions is interlaced with the plurality of neck portions along the first horizontal direction (Fig. 4).
Regarding claim 9, Wu et al. teach wherein: the plurality of laterally bulging portions has a uniform pitch along the first horizontal direction (Fig. 4); and each of the plurality of laterally bulging portions has the second width which is variable along the second horizontal direction, and a pair of laterally convex surface segments that are laterally spaced from each other along the second horizontal direction (Fig. 4).
Regarding claim 12, Wu et al. teach wherein the lateral isolation trench fill structure comprises an insulating spacer (Fig. 2, element 11A) and a conductive fill structure (Fig. 2, element 11B) that is laterally surrounded by the insulating spacer.
Regarding claim 14, Wu et al. teach wherein the insulating spacer comprises: a pair of outer lengthwise sidewalls each comprising a plurality of laterally-convex surface segments that are interlaced with a plurality of first laterally-straight surface segments; and a pair of inner lengthwise sidewalls each comprising a plurality of laterally-concave surface segments that are interlaced with a plurality of second laterally-straight surface segments (Figs. 2 & 4).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-7, 15 are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (CN 114975467 A) in view of Zhou et al. (US 2024/0349500).
Regarding claim 2, Wu et al. teach wherein: the memory opening fill structures are located in a memory array region (Fig. 2, element M1); and the plurality of laterally bulging portions is located at least in a transition region (Figs. 2 & 4, element M2) that is located between the memory array region and the contact region (Fig. 2, peripheral region as disclosed in the specification).
Wu et al. do not explicitly disclose layer contact via structures contacting a respective one of the electrically conductive layers and located in a contact region that is laterally offset from the memory array region along the first horizontal direction.
Zhou et al. teach a memory device comprising layer contact via structures (Fig. 12, element 86, paragraph 0155) contacting a respective one of the electrically conductive layers (Fig. 12, element 46, paragraph 0098) and located in a contact region (Fig. 12, element 300, paragraph 0070) that is laterally offset from the memory array region (Fig. 12, element 100, paragraph 0070) along the first horizontal direction.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to modify the teachings of Wu et al. according to the teachings of Zhou et al. with the motivation to provide interconnection.
Regarding claim 3, Wu et al. modified Zhou et al. teach wherein: each of the memory opening fill structures further comprises a respective drain region (Fig. 6F, element 63, paragraph 0086 of Zhou) that is contacted by a respective drain contact via structure (Fig. 12, element 88, paragraph 0102 of Zhou); and the transition region and the contact region are free of any drain contact via structure (paragraph 12 of Zhou) with the motivation to provide interconnection.
Regarding claim 4, Wu et al. modified Zhou et al. teach further comprising: first-type support pillar structures (Fig. 12, element 20, paragraph 0077 of Zhou) each vertically extending through a respective one of the pair of alternating stacks and located in the contact region and consisting essentially of at least one dielectric material (paragraph 0077 of Zhou discloses silicon oxide) with the motivation to provide structural support (paragraph 0077 of Zhou); and second-type support pillar structures (Fig. 2, element 40, specification of Wu discloses dummy channel structure) each vertically extending through a respective one of the pair of alternating stacks and located in the transition region and comprising a respective set of dielectric material layers and a respective semiconductor material layer (the dummy channel structure may comprise the same dielectric and conductive structure as real channel structure).
Regarding claim 5, Wu et al. modified Zhou et al. teach wherein: each of the plurality of laterally bulging portions is located adjacent to a respective one of the plurality of the second-type support pillar structures along the second horizontal direction (Figs. 2 & 4 of Wu); the respective vertical stack of memory elements comprises portions of a respective memory film located at levels of the electrically conductive layers; and the respective memory film has a same set of materials as and has a same thickness as the respective set of dielectric material layers (Figs. 2 & 4 of Wu).
Regarding claim 6, Wu et al. modified Zhou et al. teach wherein the plurality of laterally bulging portions are located only in the transition region and are not located in the memory array region or in the contact region (Figs. 2 & 4 of Wu).
Regarding claim 7, Wu et al. modified Zhou et al. teach wherein the plurality of interlaced laterally bulging portions and neck portions are located between a respective pair of straight surface segments that extend along the first horizontal direction in the memory array region and in the contact region (Figs. 2 & 4 of Wu).
Regarding Independent claim 15, Wu et al. teach a three-dimensional memory device, comprising:
an alternating stack of insulating layers (Fig. 2, specification discloses interlayer insulating film) and electrically conductive layers (Fig. 2, specification discloses gate layers, paragraph 0056);
memory openings (Fig. 2, element 21) vertically extending through the alternating stack in a memory array region (Fig. 2, element M1);
memory opening fill structures located in a respective one of the memory openings and comprising a respective vertical stack of memory elements (Fig. 2, elements 22 & 24) and a respective vertical semiconductor channel (Fig. 2, element 23);
a lateral isolation trench fill structure located adjacent to the alternating stack, the lateral isolation trench fill structure comprising a plurality of narrower neck portions (Fig. 4, element 111a) and wider laterally bulging portions (Fig. 4, element 112a) which alternate with the neck portions along the first horizontal direction and which are located in a transition region (Fig. 2, elements M2 & M3) between the memory array region and the contact region (Fig. 2, peripheral region as disclosed in the specification) along the first horizontal direction; and
second-type support pillar structures (Fig. 2, element 40, specification discloses dummy channel structure) each vertically extending through the alternating stack in the transition region and comprising a respective set of dielectric material layers and a respective semiconductor material layer (the dummy channel structure may comprise the same dielectric and conductive structure as real channel structure).
Wu et al. do not explicitly disclose layer contact via structures contacting a respective one of the electrically conductive layers and located in a contact region that is laterally offset from the memory array region along the first horizontal direction; first-type support pillar structures each vertically extending through the alternating stack in the contact region and consisting essentially of at least one dielectric material.
Zhou et al. teach a memory device comprising layer contact via structures (Fig. 12, element 86, paragraph 0155) contacting a respective one of the electrically conductive layers (Fig. 12, element 46, paragraph 0098) and located in a contact region (Fig. 12, element 300, paragraph 0070) that is laterally offset from the memory array region (Fig. 12, element 100, paragraph 0070) along the first horizontal direction; first-type support pillar structures (Fig. 12, element 20, paragraph 0077) each vertically extending through the alternating stack in the contact region and consisting essentially of at least one dielectric material (paragraph 0077 discloses silicon oxide).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to modify the teachings of Wu et al. according to the teachings of Zhou et al. with the motivation to provide structural support (paragraph 0077) and interconnection.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (CN 114975467 A).
Regarding claim 13, Wu et al. teach the conductive fill structure comprises discrete airgaps (Fig. 3 of another embodiment discloses air gap with the motivation to improve warp problem) located in middle of the laterally bulging portions and in middle of the neck portions; and the discrete airgaps are closed off and do not continue through interface regions between the laterally bulging portions and the neck portions along the first horizontal direction (Fig. 3).
Cited Prior Art
The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant.
Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply.
Conclusion
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/SHAHED AHMED/
Primary Examiner, Art Unit 2813
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