DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Su et al. (US 2010/0006934 A1 hereinafter referred to as “Su”).
With respect to claim 1, Su discloses, in Figs.1-15, a microelectronic device, comprising: source (54) and drain (56) regions having a first conductivity type/(N type) extending into a semiconductor substrate (20) having an opposite second conductivity type/(P type) (see Fig.14, Par.[0042] wherein an HVNMOS devices, with the conductivity types of regions 26, 28, 29 and 30, 44, 54 and 56; see Par.[0030] wherein an n-type dopant implantation is performed, forming N+ region 44 in HVNW region 26 (or shallow n-well 29); preferably, N+ region 44 comprise arsenic, phosphorous and/or other n-type dopants, and is heavily doped to a concentration of greater than about 10.sup.20/cm.sup.3. N+ region 44 acts as the contact region (also referred to as pickup regions) of HVPW region 26; since gate electrode 62 is spaced apart from N+ region 56, a high gate-drain voltage can be applied; Par.[0021] wherein substrate 20 is lightly doped with a p-type impurity, although it can also be doped with an n-type impurity); a channel region (26) having the first conductivity type/(N type) extending between the source region (44) and the drain region (56) (see Par.[0024] wherein high-voltage n-well (HVNW) regions 26 and 30 and HVPW region 28 in epitaxial layer 23); and a gate electrode (62) over the channel region (26) and having first and second portions with the second conductivity type/(P type), the first portion (62.sub.3) having a first dopant concentration, and the second portion (62.sub.4/62.sub.5) extending from the first portion toward the source region (44) and having a second higher dopant concentration, the second higher dopant concentration increasing from the first portion toward the source region (44) (see Par.[0037] wherein the p-type impurity concentration in edge portion 62.sub.3 of gate electrode 62 is 7 orders, or even 9 orders, higher than that of edge portion 62.sub.4. In an alternative embodiment, due to the diffusion of the p-type impurity from the portion 62.sub.2 into the portion 62.sub.1, portion 62.sub.5, which is directly over the inner edge 76 of STI region 36, has a p-type impurity concentration lower than that of edge portion 62.sub.3, but higher than that of edge portion 62.sub.4; the above-discussed p-type impurity concentrations in gate electrode 62 may represent the impurity concentrations of p-type impurities only, or more preferably represent the impurity concentrations of net impurity concentrations with n-type impurity concentrations deducted).
With respect to claim 2, Su discloses, in Figs.1-15, the microelectronic device, further comprising a drain drift region/(HVNW) of the first conductivity type/(N type) that extends from the drain region toward the source region under the first portion, the drain drift region having an average dopant concentration less than the average dopant concentration of the drain region (see Fig.14).
With respect to claim 3, Su discloses, in Figs.1-15, the microelectronic device as recited, wherein the channel region is a part of a DWELL (28) having the second conductivity type/(P type).
With respect to claim 4, Su discloses, in Figs.1-15, the microelectronic device, wherein the second portion has a second dopant concentration greater than 1 x 1018 cm-3 and the first portion has a first dopant dose less than 1 x 1013 cm-2 (see Par.[0023] wherein epitaxial layer 23 is doped with a p-type impurity; the concentration may be between about 10.sup.14/cm.sup.3 and about 10.sup.17/cm.sup.3).
Claims 1-3, 6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Koshimizu et al. (US 2022/0393027 A1 hereinafter referred to as “Koshimizu”).
With respect to claim 1, Koshimizu discloses, in Figs.01-19, a microelectronic device, comprising: source (21) and drain (20) regions having a first conductivity type/(N type) extending into a semiconductor substrate (1A) having an opposite second conductivity type/(P type) (see Par.[0047] wherein a drain region 20 made of a high concentration n-type semiconductor region is formed in the drift layer 11; on the other hand, in the p-type body region 12, a source region 21 formed of a high concentration n-type semiconductor region; see Par.[0089] wherein the p-type body region 12 is formed by implanting boron, which is a p-type impurity (acceptor), into the SOI substrate 1A); a channel region (11) having the first conductivity type/(N type) extending between the source region (21) and the drain (20) region (see Par.[0044] wherein a drift layer 11 which is an n-type semiconductor layer formed in the semiconductor substrate 1 and a p-type body region 12 which is a p-type semiconductor region in contact with the drift layer 11); and a gate electrode (16) over the channel region (12) and having first (18) and second (17) portions with the second conductivity type/(P type), the first portion (18) having a first dopant concentration, and the second portion (17) extending from the first portion toward the source region and having a second higher dopant concentration, the second higher dopant concentration increasing from the first portion toward the source region (see Par.[0045] wherein the field plate portion 16 is configured by a semiconductor region, and is configured by a high concentration p-type semiconductor region 17, a low concentration p-type semiconductor region 18 having a lower impurity concentration than the high concentration p-type semiconductor region 17, and a high concentration n-type semiconductor region 19; the low concentration p-type semiconductor region 18 is arranged so as to be sandwiched between the high concentration p-type semiconductor region 17 and the high concentration n-type semiconductor region 19).
With respect to claim 2, Koshimizu discloses, in Figs.01-19, the microelectronic device, further comprising a drain drift region (11) of the first conductivity type/(N type) that extends from the drain region (20) toward the source region (21) under the first portion, the drain drift region having an average dopant concentration less than the average dopant concentration of the drain region.
With respect to claim 3, Koshimizu discloses, in Figs.01-19, the microelectronic device, wherein the channel region is a part of a DWELL (12) having the second conductivity type.
With respect to claim 6, Koshimizu discloses, in Figs.01-19, the microelectronic device, wherein a third portion of the gate electrode extends from the second portion towards the source region, the third portion (19) having the first conductivity type/(N type) (see Par.[0045] wherein the field plate portion 16 is configured by a semiconductor region, and is configured by a high concentration p-type semiconductor region 17, a low concentration p-type semiconductor region 18 having a lower impurity concentration than the high concentration p-type semiconductor region 17, and a high concentration n-type semiconductor region 19 ).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5 are rejected under 35 U.S.C. 103 as being unpatentable over Ji (US 2023/0023179 A1) in view Koshimizu.
With respect to claim 1, Ji discloses, in Figs.1-16, a microelectronic device, comprising: source (90) and drain (91) regions having a first conductivity type/(N type) extending into a semiconductor substrate (10) having an opposite second conductivity type/(P type); a channel region (50) having the first conductivity type/(N type) extending between the source region (90) and the drain region (91) (see Par.[0047] wherein a semiconductor device including a P-type body region 30 and an N-type drift region 50 formed in a substrate 10; a highly doped source region 90 formed in the P-type body region 30; and a highly doped drain region 91 formed in the N-type drift region 50); and a gate electrode (72) over the channel region (50) and having first (72) and second (71) portions with the second conductivity type, the first portion (72) having a first dopant concentration, and the second portion (71) extending from the first portion toward the source (90) region and having a second higher dopant concentration, the second higher dopant concentration increasing from the first portion toward the source region (see Par.[0047] wherein the gate electrode 70 may include a high concentration doping region 71 and a high resistance region 72; a dopant concentration of the high concentration doping region 71 may be higher than that of the high resistance region 72; the high concentration doping region 71 may be overlapped with the P-type body region 30, and the high resistance region 72 may be overlapped with the N-type drift region 50; see Par.[0096] wherein he high concentration doping region 71 may be formed in the gate electrode 70; it may be desirable that the high concentration doping region 71 of the gate electrode 70 has a higher doping concentration than the high resistance region 72; it may be higher about 5 to 6 orders, based on a dopant concentration. When the high concentration doping region 71 has 1E19-1E21/cm.sup.3, the high resistance region 72 may have a lower concentration, 1E13-1E17/cm.sup.3). However, Ji does not explicitly teach that a gate electrode over the channel region and having first and second portions with the second conductivity type.
Koshimizu discloses, in Figs.01-19, a microelectronic device, comprising: source (21) and drain (20) regions having a first conductivity type/(N type) extending into a semiconductor substrate (1A) having an opposite second conductivity type/(P type) (see Par.[0047] wherein a drain region 20 made of a high concentration n-type semiconductor region is formed in the drift layer 11; on the other hand, in the p-type body region 12, a source region 21 formed of a high concentration n-type semiconductor region; see Par.[0089] wherein the p-type body region 12 is formed by implanting boron, which is a p-type impurity (acceptor), into the SOI substrate 1A); a channel region (11) having the first conductivity type/(N type) extending between the source region (21) and the drain (20) region (see Par.[0044] wherein a drift layer 11 which is an n-type semiconductor layer formed in the semiconductor substrate 1 and a p-type body region 12 which is a p-type semiconductor region in contact with the drift layer 11); and a gate electrode (16) over the channel region (12) and having first (18) and second (17) portions with the second conductivity type/(P type), the first portion (18) having a first dopant concentration, and the second portion (17) extending from the first portion toward the source region and having a second higher dopant concentration, the second higher dopant concentration increasing from the first portion toward the source region (see Par.[0045] wherein the field plate portion 16 is configured by a semiconductor region, and is configured by a high concentration p-type semiconductor region 17, a low concentration p-type semiconductor region 18 having a lower impurity concentration than the high concentration p-type semiconductor region 17, and a high concentration n-type semiconductor region 19; the low concentration p-type semiconductor region 18 is arranged so as to be sandwiched between the high concentration p-type semiconductor region 17 and the high concentration n-type semiconductor region 19).
Ji and Koshimizu are analogous art because they are all directed to a semiconductor device, and one of ordinary skill in the art would have had a reasonable expectation of success by modifying Ji to include Koshimizu because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the doping type of gate portions in Ji by including P type dopant type as taught by Koshimizu in order to utilize optimized gate doping by enhancing channel inversion, improving carrier density, and reducing parasitic resistance.
With respect to claim 2, Ji discloses, in Figs.1-16, the microelectronic device, further comprising a drain drift region (50) of the first conductivity type/(N type) that extends from the drain region (91) toward the source region (90) under the first portion, the drain drift region (50) having an average dopant concentration less than the average dopant concentration of the drain region (see Par.[0047] wherein a semiconductor device including a P-type body region 30 and an N-type drift region 50 formed in a substrate 10; a gate electrode 70 formed on the P-type body region 30 and the N-type drift region 50; a spacer 80 formed on a side of the gate electrode 70; a highly doped source region 90 formed in the P-type body region 30; and a highly doped drain region 91 formed in the N-type drift region 50).
With respect to claim 3, Ji discloses, in Figs.1-16, the microelectronic device, wherein the channel region is a part of a DWELL (30) having the second conductivity type/(P type) (see Par.[0047] wherein a semiconductor device including a P-type body region 30 and an N-type drift region 50 formed in a substrate 10; a gate electrode 70 formed on the P-type body region 30 and the N-type drift region 50; a spacer 80 formed on a side of the gate electrode 70; a highly doped source region 90 formed in the P-type body region 30; and a highly doped drain region 91 formed in the N-type drift region 50).
With respect to claim 5, Ji discloses, in Figs.1-16, the microelectronic device as recited, further comprising a silicide (110) blocking layer over the first portion of the gate electrode (see Par.[0059] wherein silicide blocking insulating films 81, 100 and 101 Silicide blocking insulating films 81, 100 and 101 may be formed around a gate electrode; the silicide blocking insulating films 81, 100 and 101 may inhibit forming silicide films 110, 120 and 121).
Allowable Subject Matter
Claims 7-20 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claims 7, 14, a method of forming a microelectronic device, comprising: none of the prior art of record teaches, suggests or renders obvious, either alone or in combination, thermally annealing the gate electrode such that the dopant of the second conductivity type in the second portion of the gate electrode diffuses toward the first end thereby providing a horizontal gradient of the dopant in the second portion. Claims 8-13 and 15-20 are also allowed because of their dependency to the allowed base claims 7, 14.
Citation of Pertinent Prior Art
The prior art made of record (e.g.; see PTO-892) and not relied upon is considered pertinent to applicant's disclosure.
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Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOULOUCOULAYE INOUSSA whose telephone number is (571)272-0596. The examiner can normally be reached Monday-Friday (10-18).
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/Mouloucoulaye Inoussa/ Primary Examiner, Art Unit 2818