DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention II in the reply filed on 2/2/2026 is acknowledged.
Claims 1-8 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 2/2/2026.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 9-23 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Makino (US 2016/0254214; hereinafter Makino).
Regarding claim 9, Figs 2A, 3, 5 and 10 of Makino discloses a package comprising:
a die pad (DP; Fig 5; ¶ [0066]) exposed to a bottom surface (MRb; Fig 5; ¶ [0068]) of the package (¶ [0070]);
a semiconductor die (CHP; Fig 5; ¶ [0066]) coupled to the die pad (DP; Fig 5; ¶ [0066]);
a conductive terminal (LD; Figs 4-5; ¶ [0066]) coupled to the semiconductor die (CHP; Fig 5; ¶ [0066]), the conductive terminal comprising:
a first surface (LDb; Figs 4-5; ¶ [0072]) exposed to the bottom surface (MRb; Fig 5; ¶ [0068]) of the package;
a second surface (LDs; Figs 4-5; ¶ [0074]) exposed to a lateral surface (MRs; Fig 5; ¶ [0068]) of the package that is orthogonal (Fig 5) to the bottom surface (MRb; Fig 5; ¶ [0068]) of the package; and
a third surface (LDd/LDg; Fig 5; ¶ [0078]) extending from the first surface (LDb; Figs 4-5; ¶ [0072]) toward the second surface (LDs; Figs 4-5; ¶ [0074]), the third surface (LDd/LDg; Fig 5; ¶ [0078]) meeting the first surface (LDb; Figs 4-5; ¶ [0072]) along an edge (Fig 5) of the first surface, the edge extending substantially parallel to the lateral surface of the package (Fig 5); and
a mold compound member (MR; Fig 5; ¶ [0068]) extending between the conductive terminal (LD; Figs 4-5; ¶ [0066]) and a second conductive terminal (LD; Figs 4-5; ¶ [0066]), wherein the mold compound member includes a side surface (Fig 3) that is orthogonal to the lateral and bottom surfaces of the package, and wherein at least a portion of the side surface is not covered by the conductive terminal (Fig 3).
Regarding claim 10, Figs 2A, 3, 5 and 10 of Makino discloses the package is a quad flat no lead (QFN) package (¶ [0063]).
Regarding claim 11, Figs 2A, 3, 5 and 10 of Makino discloses the third surface (LDd/LDg; Fig 5; ¶ [0078]) is a curved surface (Figs 3-5).
Regarding claim 12, Figs 2A, 3, 5 and 10 of Makino discloses the first surface (LDb; Figs 4-5; ¶ [0072]) is substantially flush (Fig 5) with the bottom surface (MRb; Fig 5; ¶ [0068]).
Regarding claim 13, Figs 2A, 3, 5 and 10 of Makino discloses the second surface (LDs; Figs 4-5; ¶ [0074]) is substantially flush with the lateral surface (MRs; Fig 5; ¶ [0068]).
Regarding claim 14, Figs 2A, 3, 5 and 10 of Makino discloses the first (LDb; Figs 4-5; ¶ [0072]) and third surfaces (LDd/LDg; Fig 5; ¶ [0078]) are plated with tin. (¶ [0083])
Regarding claim 15, Figs 2A, 3, 5 and 10 of Makino discloses the second surface (LDs; Figs 4-5; ¶ [0074]) is not plated with tin. (Fig 5)
Regarding claim 16, Figs 2A, 3, 5 and 10 of Makino discloses the first (LDb; Figs 4-5; ¶ [0072]) and third surfaces (LDd/LDg; Fig 5; ¶ [0078]) are plated and the second surface (LDs; Figs 4-5; ¶ [0074]) is not plated.
Regarding claim 17, Figs 2A, 3 and 4 of Makino discloses a second mold compound member (MR; Fig 2A) extending between the conductive terminal (LD; Figs 4-5; ¶ [0066]) and a third conductive terminal (LD; Figs 4-5; ¶ [0066]), the conductive terminal positioned between the second and third conductive terminals (Fig 2A), wherein:
the second mold compound member (MR; Fig 2A/3) includes a second side surface that is orthogonal to the lateral and bottom surfaces of the package (Fig 3),
at least a portion of the second side surface is not covered by the conductive terminal, and the side surface and the second side surface face each other. (Fig 3)
Regarding claim 18, Figs 2A, 3 and 4 of Makino discloses the edge is not curved (Fig 5).
Regarding claim 19, Figs 2A, 3, 5 and 10 of Makino discloses a package
a semiconductor die (CHP; Fig 5; ¶ [0066]); and
a conductive terminal (LD; Figs 4-5; ¶ [0066]) coupled to the semiconductor die (CHP; Fig 5; ¶ [0066]), the conductive terminal comprising:
a first surface (LDb; Figs 4-5; ¶ [0072]) substantially flush with a bottom surface (MRb; Fig 5; ¶ [0068]) of the package;
a second surface (LDs; Figs 4-5; ¶ [0074]) substantially flush with a lateral surface (MRs; Fig 5; ¶ [0068]) that isorthogonal (Fig 5) to the bottom surface (MRb; Fig 5; ¶ [0068]) of the package; and
a curved surface (LDd/LDg; Fig 5; ¶ [0078]) extending from the first surface (LDb; Figs 4-5; ¶ [0072]) to the second surface (LDs; Figs 4-5; ¶ [0074]), the curved surface (LDd/LDg; Fig 5; ¶ [0078]) meeting the first surface (LDb; Figs 4-5; ¶ [0072]) along a first edge (Fig 5) and meeting the second surface along a second edge, the first and second edges parallel to the lateral surface (Fig 5).
Regarding claim 20, Figs 2A, 3, 5 and 10 of Makino discloses the first and second edges are not curved (Fig 5).
Regarding claim 21, Regarding claim 16, Figs 2A, 3, 5 and 10 of Makino discloses the first (LDb; Figs 4-5; ¶ [0072]) and curved surfaces (LDd/LDg; Fig 5; ¶ [0078]) are plated with tin (¶ [0083]) and the second surface (LDs; Figs 4-5; ¶ [0074]) is not plated with tin.
Regarding claim 22, Figs 2A, 3, 5 and 10 of Makino discloses the first (LDb; Figs 4-5; ¶ [0072]) and curved surfaces (LDd/LDg; Fig 5; ¶ [0078]) are plated and the second surface (LDs; Figs 4-5; ¶ [0074]) is not plated.
Regarding claim 23, Figs 2A, 3, 5 and 10 of Makino discloses the package is a quad flat no lead (QFN) package (¶ [0063]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Kasahara et al (US 2016/0181187)
Bai et al (US 2016/0056097)
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RATISHA MEHTA whose telephone number is (571)270-7473. The examiner can normally be reached Monday-Friday: 9:00am - 5:00 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos Feliciano can be reached at 571-272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/RATISHA MEHTA/Primary Examiner, Art Unit 2817
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