DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election, with traverse, of Group 1: claims 1-15 in “Response to Election / Restriction Filed - 05/27/2026”, is acknowledged.
Applicant’s traversal submittal requesting that claims in Group II that correspond to allowable Group I claims be reinstated for allowance. It is understood that Applicant is requesting for the rejoinder of the non-elected claims upon allowance of the elected claims, that will be given due consideration as required in in MPEP § 821.04(b).
The restriction requirement is still deemed proper, and is therefore made FINAL, and thus the required provisional election (see MPEP § 818.03(b)) becomes an election without traverse.
In view of the above, this office action considers claims 1-18 pending for prosecution, of which, non-elected claims 16-18 are withdrawn, and elected claims 1-15 are examined on their merits.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as 20; Fig 1A; [0033]) = (element 20; Figure No. 1A; Paragraph No. [0033]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. The primary reference, in this case Yamaguchi. citation may not be preceded by the inventor tag, wherein the other reference citation will carry inventor tag. These conventions are used throughout this document.
Claims 1-6 and 8-15 are rejected under 35 U.S.C. 102 (a) (1) as being anticipated by Yamaguchi, Yukio et al. (US 20030003627 A1) hereinafter Yamaguchi.
Regarding Claim 1. Yamaguchi teaches a semiconductor device (labelled as “a resin-sealed type semiconductor device”; Fig 12; Fig 1A depict Wire connectivity and detailed parts [0032-0033)) comprising (see the entire document, Figs 12/1A and 1B/13, along with other figs referenced subject matter for details, specifically, as cited below):
PNG
media_image1.png
360
1392
media_image1.png
Greyscale
Yamaguchi Fig 12 Fig 1, depicting wire connection
a semiconductor element (labelled as semiconductor chip 20; Fig 12/1A; [0033]) including an element body (all of 20, except periphery) containing a semiconductor and a first electrode (electrode pad 21; [0033]) disposed on the element body;
a first lead (die pad 11) on which the semiconductor element (20) is mounted;
a second lead (14a; at left side 20; Fig 12); and
a first wire (25) electrically connecting the semiconductor element (20) and the second lead (the 14a; at left side 20; Fig 12), wherein
the first lead (die pad 11) includes a die pad portion (die pad portion underlying 17) including a die-pad obverse surface (top surface of die pad 11, not covered by 17) and a die-pad reverse surface (bottom surface of die pad 11 away from 17/20) facing away from each other in a thickness direction (vertical),
the semiconductor element (the semiconductor chip 20) is mounted on the die-pad obverse surface (the top surface of die pad 11 nearest to 17),
the second lead (the 14a; at left side 20; Fig 12/1A) includes a bonding pad portion (portion of 14a overlying Phe/51) including a bonding-pad obverse surface (top surface of 14a overlying Phe/51) facing a same side as the die-pad obverse surface (the top surface of die pad 11 nearest to 17) in the thickness direction and a bonding-pad reverse surface (bottom surface of 14a overlying Phe/51) facing away from the bonding-pad obverse surface,
the bonding-pad reverse surface (bottom surface of 14a) is offset from the die-pad reverse surface (bottom surface of die pad 11 away from 17) toward the die-pad obverse surface-side (top surface of die pad 11) in the thickness direction ([0090] die pad 11 higher than other parts of the lead frame),
the first wire (25) is bonded to the first electrode (electrode pad 21; [0033] as depicted in fig 12/1A) and the bonding-pad obverse surface (the top surface of 14a overlying Phe/51), and
the bonding pad portion (portion of 14a overlying Phe/51; Figs 5a to 13) includes a single first portion (portion of 14a overlying 51 Figs 5a to 13), the first portion (portion of 14a overlying 51 Figs 5a to 13) being connected to the bonding-pad reverse surface (the surface overlying 51), surrounded by the bonding-pad reverse surface (bottom surface of 14a) as viewed in the thickness direction, and including a part (surface between 14a and 51) present at a position different from the bonding-pad reverse surface (bottom surface of 15A) in the thickness direction (Vertical).
Regarding Claim 2. Yamaguchi as applied to the semiconductor device according to claim 1, further teaches, wherein the first wire (25; Figs 12. 1A; [0078]) includes a bonding portion (portion of 14a overlying Phe/51; Figs 5a to 13) bonded to the bonding-pad obverse surface (top surface), and
at least a part of the bonding portion (portion of 14a overlying Phe/51; Figs 5a to 13) and at least a part of the first portion (portion of 14a overlying 51; Figs 5a to 13) overlap with each other as viewed in the thickness direction.
Regarding Claim 3. Yamaguchi as applied to the semiconductor device according to claim 2, further teaches, wherein the bonding portion (14a) is a second bonding portion (because of its location on second lead).
Regarding Claim 4. Yamaguchi as applied to the semiconductor device according to claim 1, further teaches, wherein the first portion (portion of 14a/15a overlying 51 Figs 5a to 13) is a recess ( a vacuuming hole 52 near the projection 51; Fig 11; [0087]) including an opening edge (adjacent to 40) in the bonding-pad reverse surface .
Regarding Claim 5. Yamaguchi as applied to the semiconductor device according to claim 4, further teaches, wherein portions of the recess (52) other than the opening edge are located inward from the opening edge as viewed in the thickness direction (Figs 11-12).
Regarding Claim 6. Yamaguchi as applied to the semiconductor device according to claim 5, further teaches, wherein the recess ( a vacuuming hole 52 near the projection 51; Fig 11; [0087]) includes a first surface (52) inclined to become farther away from the bonding-pad reverse surface as viewed in the thickness direction as proceeding farther away from the bonding-pad reverse surface in the thickness direction.
Regarding Claim 8. Yamaguchi as applied to the semiconductor device according to claim 6, further disclose, wherein the first surface (52 in Fig 12) has a shape of a loop (U-shaped) as viewed in the thickness direction.
Regarding Claim 9. Yamaguchi as applied to the semiconductor device according to claim , further teaches, wherein the recess ( a vacuuming hole 52 near the projection 51; Fig 11; [0087]) includes a second surface inclined to become farther away from the bonding-pad (towards bottom along 52) reverse surface as viewed in the thickness direction as proceeding farther away from the bonding-pad reverse surface in the thickness direction and disposed at a position different from the first surface as viewed in the thickness direction.
Regarding Claim 10. Yamaguchi as applied to the semiconductor device according to claim 1, further teaches, wherein the first portion (15a/15b) is a protrusion (Fig 12) that protrudes from the bonding-pad reverse surface (bottom of 14a).
Regarding Claim 11. Yamaguchi as applied to the semiconductor device according to claim 1, further teaches, (the device) further comprising a sealing resin (30; ; Fig 2d; [0040]) covering the semiconductor element, the first wire, and a part of each of the first lead and the second lead (14a).
Regarding Claim 12. Yamaguchi as applied to the semiconductor device according to claim 11, further teaches, wherein the first portion (portion of 14a/15a overlying 51) is covered ([0040]) with the sealing resin (30).
Regarding Claim 13. Yamaguchi as applied to the semiconductor device according to claim 12, further teaches, wherein the second lead (14a at left ; fig 12) includes a terminal portion (15a/15b; [0033]) exposed from the sealing resin (30) and offset from the bonding pad portion toward a side which the bonding-pad reverse surface (bottom of 14a) faces in the thickness direction.
Regarding Claim 14. Yamaguchi as applied to the semiconductor device according to claim 13, further teaches, wherein at least a part of the terminal portion (15a/15b) and at least a part of the die pad portion (11) overlap (Fig 5a) with each other as viewed in a direction orthogonal (lateral) to the thickness direction (vertical).
Regarding Claim 15. Yamaguchi as applied to the semiconductor device according to claim 14, further teaches, wherein the second lead includes a connecting portion (along Phe) interposed between the bonding pad portion (14a) and the terminal portion (15a/15b) and having a bent shape.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:uu
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
laim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Yamaguchi, Yukio et al. (US 20030003627 A1) hereinafter Yamaguchi.
Regarding Claim 7. Yamaguchi as applied to the semiconductor device according to claim 6, does not expressly disclose, wherein a first angle formed between the first surface (52) and a plane orthogonal to the thickness direction is equal to or greater than 25° and equal to or less than 50°.
However, the Applicant has not presented persuasive evidence that the claimed “a first angle formed between the first surface (52) and a plane orthogonal to the thickness direction is equal to or greater than 25° and equal to or less than 50” is for a particular purpose that is critical to the overall claimed invention (i.e. the invention would not work without a sidewall (52) with Z-Y plane of the angle 25 to 50 degree), Also, the Applicant has not shown that “a first angle formed between the first surface (52) and a plane orthogonal to the thickness direction is equal to or greater than 25” produces a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art. Instead, paragraph [0052] discloses other possible options such as “the shape and size of the first surface 2131 are not particularly limited”. Therefore, no rationale given that the invention will not function without “a sidewall (52) with Z-Y plane of the angle 25 to 50 degree”. Thus, the claimed wherein a sidewall (52) with Z-Y plane of the angle 25 to 50 degree is not critical to the invention.
Examiner would like to note that MPEP §2144.04.IV(B) guideline, where change of shape is a Legal Precedent as Source of Supporting Rationale. See In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966) (The court held that the configuration of the claimed disposable plastic nursing container was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed container was significant. .
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOAZZAM HOSSAIN whose telephone number is (571)270-7960. The examiner can normally be reached M-F: 8:30AM - 6:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio J. Maldonado can be reached on 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MOAZZAM HOSSAIN/Primary Examiner, Art Unit 2898
June 12, 2026
Prosecution Insights