DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, Species 3 (Fig. 3) (claims 1-4, 6-10) in the reply filed on 03/30/2026 is acknowledged.
Claims 5, 11-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 3/30/26.
Claim Objections
Claim 1 is objected to because of the following informalities: “a insulating..” should be “an insulating ..” Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6-10 are rejected under 35 U.S.C. 103 as being obvious over KR 100872265 B1 (herein after refer to ‘2265) in view of Pagalia et al (US 2009/0302478 A1) and Nathapong et al. (US PGPUB 2015/0102478 A1)
Regarding claim 1: ‘2265 teaches in Fig. 3e about a semiconductor package comprising:
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a semiconductor wafer 10 having a first connection pad 31 (left one) and a second connection pad 31 (right one) spaced apart by a semiconductor region (where 30 resides) of the semiconductor wafer, wherein portions of the semiconductor wafer are covered by a protective overcoat 11;
a cap wafer 20 mounted to the semiconductor wafer and overpassing the semiconductor region of the semiconductor wafer, wherein the cap wafer extends between the first connection pad and the second connection pad of the semiconductor wafer (as shown); and
a insulation material overlaying the cap wafer, the insulation material comprising vias 60’s to the first connection pad and the second connection pad, the vias being filled with a conductive material (Al or Cu can be filled).
‘2265 does not explicitly show a insulation material overlaying the cap wafer, the insulation material comprising vias.
Pagalia teaches in Fig. 8 about a insulation material (296 or 300 or 296+300) overlaying the cap wafer 290, the insulation material comprising vias 296.
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Nathapong also teaches in Fig. 1 about a insulation material 117 overlaying the cap wafer ([0019] teaches 15 is sealed under a cap layer over which the insulating material 117), the insulation material comprising vias (where 146 resides).
Thus, it would have been obvious to one of the ordinary skill in the art at the time the application was filled to have a insulation material overlaying the cap wafer, the insulation material comprising vias in ‘2265’s device according to the teachings of Pagalia and Nathapong to cover active surfaces of the device for protection from electrical short as a general practice in the semiconductor packaging.
Regarding claim 2: ‘2265 in Fig. 3e and Pagalia in Fig. 8 teaches wherein the vias of the insulation material are tapered with a wider opening at an end distal from the first connection pad and the second connection pad.
Regarding claim 3: Pagalia teaches in Fig. 8 further comprising a molding 316 encapsulating the semiconductor wafer, the cap wafer and the insulation material.
Regarding claim 4: ‘2265 teaches wherein the conductive material filling the vias is copper.
Regarding claim 6: Pagalia teaches in Fig. 8 further comprising wire bonding 312 between ends of the copper in the vias and leads of an interconnect 310.
Thus, it would have been obvious to one of the ordinary skill in the art at the time the application was filled to have the feature as claimed in ‘2265’s device according to the teachings of Pagalia to connect to external connection.
Regarding claim 7: ‘2265 tin page 2 and Nathapong in [0018] teaches wherein the semiconductor region of the semiconductor wafer comprises resonator.
Regarding claim 8: Nathapong in [0012] teaches wherein the semiconductor package is a stress sensor.
It has been held that a recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus satisfying the claimed structural limitations. Ex parte Masham, 2 USPQ 2d 1647 (1987).
Regarding claim 9: ‘2265 teaches in Fig. 3e, wherein the taper of the vias has an angle between 30 degrees and 89 degrees.
Regarding claim 10: Pagaila teaches in [0042] wherein the insulation material is polyimide, PBO or SU-8.
It would have been obvious to one of ordinary skill in the art at the time of the application was filed to have the material as claimed as an insulating material, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED SHAMSUZZAMAN whose telephone number is (571)270-1839. The examiner can normally be reached Monday-Friday 7 am -4 pm EST.
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/Mohammed Shamsuzzaman/Primary Examiner, Art Unit 2897