DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 7-8, 11-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to nonelected species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 3/4/2026.
Applicant's election with traverse of Species A in the reply filed on 3/4/2026 is acknowledged. The traversal is on the ground(s) that 3/4/2026. This is not found persuasive because the traversal is based on the unsupported assertion that there are common elements in the identified species that would “naturally be found” in the search of any one species. A proper traversal of a species restriction requires either 1) Applicant admits on the record that the independent species are obvious variants in which case any art which reads on one species would be used to reject all the species, or 2) Applicant provides a single reference which teaches all species (see Section 8. In Requirement for Restriction/Election mailed 3/2/2026). As applicant has not provided a reference nor statement of obviousness the traversal is unpersuasive.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-6, and 9-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20240145578 A1 (Vega) further in view of US 20210098473 A1 (Lin).
Re claims 1 and 2 and 3, Vega teaches a semiconductor device comprising:
a substrate including a first region and a second region (see annotated Fig. 1A wherein when the first region contains NFETs the second region contains PFETs and when the first region contains PFETs the second region contains NFETs);
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a plurality of first bridge patterns (channel region layers 108 in the PFETs in the first region) sequentially stacked on the first region and spaced apart from each other (Fig. 15), the plurality of first bridge patterns extending in a first direction (X direction see annotated Fig. 15);
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a first gate structure (gate structure 902 including sidewall spacers 704) extending in a second direction (Z direction see annotated Fig. 1A) intersecting the first direction, the plurality of first bridge patterns penetrating through the first gate structure (Fig. 15);
a first epitaxial pattern (epitaxial layers 802 in PFETs in first region) connected to the plurality of first bridge patterns and on a side surface of the first gate structure, the first epitaxial pattern including a first impurity having a first conductivity type (when the nanosheet transistor is PFET the epitaxial layers are p-type [0055]);
a first silicide pattern (source/drain metal contacts 1502 form a silicide at the interface of the epitaxial layer and the metal [0063]) on the first epitaxial pattern and overlapping the plurality of first bridge patterns in the first direction (Fig. 15);
a plurality of second bridge patterns (channel region layers 108 in the NFETs in the second region) sequentially stacked on the second region, and spaced apart from each other (Fig. 15), the plurality of second bridge patterns extending in a third direction (X direction);
a second gate structure (gate structure 902 including sidewall spacers 704) extending in a fourth direction (Z direction) intersecting the third direction, the plurality of second bridge patterns penetrating through the second gate structure (Fig. 15);
a second epitaxial pattern (epitaxial layers 802 in PFETs in first region) connected to the plurality of second bridge patterns and on a side surface of the second gate structure, the second epitaxial pattern including a second impurity having a second conductivity type different from the first conductivity type (when the nanosheet transistor is PFET the epitaxial layers are p-type [0055]); and
a second silicide pattern (source/drain metal contacts 1502 form a silicide at the interface of the epitaxial layer and the metal [0063]) on the second epitaxial pattern and overlapping the plurality of second bridge patterns in the third direction (Fig. 15).
Vega does not explicitly teach wherein the first silicide pattern and the second silicide pattern have stress properties different from each other (claim 1), nor wherein the first conductivity type is a p-type, the second conductivity type is an n-type, and the second silicide pattern has greater tensile stress properties than the first silicide pattern (claim 2), nor wherein the first silicide pattern has compressive stress properties, and the second silicide pattern has tensile stress properties (claim 3).
Lin teaches nanosheet NFETs and PFETs wherein the epitaxial layers for the source/drain regions of the NFETs are preferably made of materials having a lattice constant smaller than that of the channel in order to induce tensile stress in the channel layers and wherein the epitaxial layers for the source/drain regions of the PFETs are preferably made of materials having a lattice constant larger than that of the channel in order to induce compressive stress in the channel layers ([0050]). Lin also teaches forming silicides on the epitaxial layers making up the source/drain features ([0050]).
It would have been obvious at the time of filing to form the epitaxial layers of strain inducing materials according the type of device being made.
The motivation to do so is that channel strain engineering using SiGe or Si:C source/drain regions provides the predictable result of increasing carrier mobility in the channel. For NFETs electron mobility is increased using tensile stress and in PFETs hole mobility is increased using compressive stress. Vega teaches that the silicide is formed by a silicidation of the interface of the metal/epitaxial layer interface therefore the straining effects in the silicide in the NFET with Si:C source/drain epitaxial region would help impart tensile stress in the channel layers and the silicide in the PFET with SiGe source/drain epitaxial region would help impart compressive stress in the channel layers.
Re claim 4, Vega teaches wherein the first epitaxial pattern comprises a first epitaxial trench overlapping the plurality of first bridge patterns in the first direction, the first silicide pattern fills at least a part of the first epitaxial trench, the second epitaxial pattern comprises a second epitaxial trench overlapping the plurality of second bridge patterns in the third direction, and the second silicide pattern fills at least a part of the second epitaxial trench (Fig. 15).
Re claim 5, Vega teaches wherein the first epitaxial trench extends in the second direction, and the second epitaxial trench extends in the fourth direction (the trenches have a width that extends in the Z direction see annotated Fig. 1A and Fig. 15).
Re claim 6, Vega teaches wherein the first silicide pattern covers an upper surface of the first epitaxial pattern, and the second silicide pattern covers an upper surface of the second epitaxial pattern (Vega teaches that the source/drain metal contacts can be formed on the front side of the IC [0057] which would result in the silicide being on the top surface of the epitaxial patterns).
Re claim 9, Vega teaches further comprising: a first source/drain contact (metal portion of source/drain metal contacts 1502 in PFETs) on the first silicide pattern and connected to an upper surface of the first silicide pattern; and a second source/drain contact (metal portion of source/drain metal contacts 1502 in NFETs) on the second silicide pattern and connected to an upper surface of the second silicide pattern (Vega teaches that the source/drain metal contacts can be formed on the front side of the IC [0057] which would result in the metal portion being on the top surface of the silicide).
Re claim 10, Vega teaches wherein a concentration of the first impurity decreases as a distance from the first silicide pattern increases, and a concentration of the second impurity decreases as a distance from the second silicide pattern increases (since the silicide is formed by silicidation (i.e. alloying) of the metal and doped epitaxial layers the dopants it is obvious that the dopant concentration will be highest in the epitaxial layer and will be lower in the silicide and then completely absent from the metal).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20230402459 A1 (Jeong)
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US 20230178621 A1 (Xie)
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US 20220359208 A1 (Lin)
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US 20230290862 A1 (Hall)
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Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIGITTE A PATERSON whose telephone number is (571)272-1752. The examiner can normally be reached Monday-Friday 9:00AM-5:00PM.
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BRIGITTE A. PATERSON
Primary Examiner
Art Unit 2896
/BRIGITTE A PATERSON/Primary Examiner, Art Unit 2896
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