DETAILED ACTION
In response to communications filed 04/03/2026.
Claims 1-20 are pending for examination.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claims 8 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Examiner has been unable to locate prior art that reasonably, either singularly or in combination with cited references, would result a proper rejection that would have anticipated or made obvious the subject matter claimed in dependent claims 8 and 17 including all of the limitations of independent claims 1 and 11 respectively and any intervening claims with proper motivation at or before the time it was effectively filed
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-7, 9-16 and 18-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lin et al. (US 2016/0309343 A1) hereinafter “Lin.”
Regarding Claim 1, Lin teaches A method for error detection in a message (Lin: paragraphs 0050-0053 & Fig. 3, message) the method being performed with at least one circuit (Lin: paragraphs 0050, 0071 & Figs. 3 & 7, apparatus (i.e. transmitter and/or receiver)), the method comprising:
identifying, based on an error detection configuration of the at least one circuit (Lin: paragraph 0051, error detection code), a first portion of the message (Lin: paragraph 0050 & Fig. 3, first segment of a sequence of multiple segments of a message) to be checked for errors (Lin: paragraph 0051, error detection code for each message segment) before a second portion of the message (Lin: paragraphs 0050-0051 & Fig. 3, another segment of the message segment) is available to the at least one circuit (Lin: paragraph 0064, progression indicator bit indicates that another segment exists after decoding first segment), the first portion being less than all of the message to be checked for one or more errors (Lin: paragraph 0050 & Fig. 3, divide message into a sequence of message segments);
analyzing a number of bits of the first portion of the message using the at least one circuit and based on the error detection configuration (Lin: paragraph 0061 & Fig. 5A, bits of each message segment (i.e. message segment S)); and
based on analyzing the first portion, determining whether the message includes the one or more errors (Lin: paragraph 0051, generate error detection code for each segment).
Regarding Claim 2, Lin teaches the respective claim(s) as presented above and further teaches configuring the at least one circuit with the error detection configuration from a plurality of error detection configurations, prior to identifying the first portion of the message to be checked for the one or more errors (Lin: paragraph 0051 & Fig. 3, parity codes (e.g., cyclic redundancy check (CRC) codes) may be independently generated for each message segment independently of one another).
Regarding Claim 3, Lin teaches the respective claim(s) as presented above and further teaches wherein the number of bits is a first number of bits (Lin: paragraph 0061 & Fig. 5A, bits of first message segment S), and further comprising:
receiving, based on the error detection configuration of the at least one circuit (Lin: paragraph 0051, said error detection code for each message segment), the second portion of the message to be checked for the one or more errors (Lin: paragraphs 0050-0051 & Fig. 3, error detection for another segment of the message segment), the second portion being less than all of the message to be checked for the one or more errors (Lin: paragraph 0050 & Fig. 3, divide message into a sequence of message segments);
analyzing a second number of bits of the second portion of the message using the at least one circuit and based on the error detection configuration (Lin: paragraph 0061 & Fig. 5A, bits of each message segment (i.e. message segment S+1)); and
determining, based on analyzing of the first portion and the second portion, whether the message includes the one or more errors (Lin: paragraph 0051, generate error detection code for each segment).
Regarding Claim 4, Lin teaches the respective claim(s) as presented above and further teaches retrieving, from memory (Lin: paragraphs 0015-0016 memory), a first error detection value associated with analyzing the first portion of the message (Lin: paragraph 0061, error detection codes for message segments S);
generating an aggregate error detection value of the message from the first error detection value and a second error detection value associated with analyzing the second portion of the message (Lin: paragraph 0051 & Fig. 3, said generating error detection code for each message segment of the sequence of message segments); and
determining, based on the aggregate error detection value, whether the message includes the one or more errors (Lin: paragraphs 0051 & 0061, said error detection of each segment).
Regarding Claim 5, Lin teaches the respective claim(s) as presented above and further teaches identifying, using the at least one circuit, an initial error detection value that was generated and edited into the message (Lin: paragraph 0051, parity codes may be generated for each message segment); and
determining whether the message includes the one or more errors by comparing the aggregate error detection value to the initial error detection value in the message (Lin: paragraphs 0051 & 0061, said error detection of each segment).
Regarding Claim 6, Lin teaches the respective claim(s) as presented above and further teaches modifying the message to include the aggregate error detection value (Lin: paragraph 0051, parity codes may be generated for each message segment).
Regarding Claim 7, Lin teaches the respective claim(s) as presented above and further teaches wherein:
the error detection configuration is a first error detection configuration (Lin: paragraph 0051 & Fig. 3, parity codes (e.g., cyclic redundancy check (CRC) codes);
the number of bits is a first number of bits (Lin: paragraph 0061 & Fig. 5A, bits of first message segment S); and
the method further comprises:
configuring the at least one circuit with a second error detection configuration of a plurality of error detection configurations (Lin: paragraph 0061, error detection codes for message segments S), the plurality of error detection configurations comprising the first error detection configuration and the second error detection configuration being different from the first error detection configuration (Lin: paragraph 0051 & Fig. 3, parity codes (e.g., cyclic redundancy check (CRC) codes) may be independently generated for each message segment independently of one another);
identifying, based on the second error detection configuration of the at least one circuit, a third portion and a fourth portion of the message to be checked for the one or more errors (Lin: paragraphs 0050 & 0061, sequence of multiple segments (i.e. S+1, L, etc.)), the third portion and the fourth portion being less than all of the message to be checked for the one or more errors (Lin: paragraph 0050 & Fig. 3, divide message into a sequence of message segments);
analyzing a second number of bits of the third portion and the fourth portion of the message using the at least one circuit and based on the second error detection configuration (Lin: paragraph 0061 & Fig. 5A, bits of each message segment (i.e. message segment S, i.e. S+1, L, etc.)); and
based on analyzing the third portion and the fourth portion, determining whether the message includes the one or more errors (Lin: paragraph 0051, generate error detection code for each segment).
Regarding Claim 9, Lin teaches the respective claim(s) as presented above and further teaches wherein:
the error detection configuration is a first error detection configuration (Lin: paragraph 0051 & Fig. 3, said generating error detection code for each message segment of the sequence of message segments);
the message is a first message (Lin: paragraph 0050 & Fig. 3, message);
the number of bits is a first number of bits (Lin: paragraph 0061 & Fig. 5A, bits of first message segment S); and
the method further comprises:
configuring the at least one circuit with a second error detection configuration of a plurality of error detection configurations, the plurality of error detection configurations comprising the first error detection configuration and the second error detection configuration being different from the first error detection configuration (Lin: paragraph 0051 & Fig. 3, parity codes (e.g., cyclic redundancy check (CRC) codes) may be independently generated for each message segment independently of one another);
identifying, based on the second error detection configuration of the at least one circuit, a third portion of a second message to be checked for the one or more errors (Lin: paragraphs 0050 & 0061, sequence of multiple segments (i.e. S+1, L, etc.)), the third portion being less than all of the second message to be checked for the one or more errors (Lin: paragraph 0050 & Fig. 3, divide message into a sequence of message segments);
analyzing a second number of bits of the third portion of the second message using the at least one circuit and based on the second error detection configuration (Lin: paragraph 0061 & Fig. 5A, bits of each message segment (i.e. message segment S, i.e. S+1, L, etc.)); and
based on analyzing the third portion, determining whether the second message includes the one or more errors (Lin: paragraph 0051, generate error detection code for each segment).
Regarding Claim 10, Lin teaches the respective claim(s) as presented above and further teaches wherein:
the at least one circuit receives the third portion of the second message between the first portion of the first message and the second portion of the first message (Lin: paragraphs 0050 & 0061, sequence of multiple segments);
configuring of the at least one circuit with the second error detection configuration is performed after analyzing the first portion of the message using the at least one circuit and based on the first error detection configuration (Lin: paragraph 0051 & Fig. 3, said generating error detection code for each message segment of the sequence of message segments); and
the method further comprises:
configuring the at least one circuit with the first error detection configuration after analyzing the third portion of the second message using the at least one circuit and based on the second error detection configuration (Lin: paragraph 0051 & Fig. 3, parity codes (e.g., cyclic redundancy check (CRC) codes) may be independently generated for each message segment independently of one another).
Regarding Claim 11, Lin teaches A system for error detection in a message (Lin: paragraphs 0050-0053 & Fig. 3, message), the system comprising:
a computation circuit (Lin: paragraphs 0050, 0071 & Figs. 3 & 7, apparatus (i.e. transmitter and/or receiver)) configured to:
identify, based on an error detection configuration of the computation circuit (Lin: paragraph 0051, error detection code), a first portion of the message (Lin: paragraph 0050 & Fig. 3, first segment of a sequence of multiple segments of a message) to be checked for one or more errors (Lin: paragraph 0051, error detection code for each message segment) before a second portion of the message (Lin: paragraphs 0050-0051 & Fig. 3, another segment of the message segment) is available to the computation circuit (Lin: paragraph 0064, progression indicator bit indicates that another segment exists after decoding first segment), the first portion being less than all of the message to be checked for the one or more errors (Lin: paragraph 0050 & Fig. 3, divide message into a sequence of message segments); and
analyze a number of bits of the first portion of the message based on the error detection configuration (Lin: paragraph 0061 & Fig. 5A, bits of each message segment (i.e. message segment S)); and
a modification circuit configured to, based on analyzing the first portion, determine whether the message includes the one or more errors (Lin: paragraph 0051, generate error detection code for each segment).
Regarding Claim 12, Lin teaches the respective claim(s) as presented above and further teaches wherein the computation circuit is further configured with the error detection configuration from a plurality of error detection configurations, prior to identifying the first portion of the message to be checked for the one or more errors (Lin: paragraph 0051 & Fig. 3, parity codes (e.g., cyclic redundancy check (CRC) codes) may be independently generated for each message segment independently of one another).
Regarding Claim 13, Lin teaches the respective claim(s) as presented above and further teaches wherein:
the computation circuit is further configured to:
receive, based on the error detection configuration of the computation circuit (Lin: paragraph 0051, said error detection code for each message segment), the second portion of the message to be checked for the one or more errors(Lin: paragraphs 0050-0051 & Fig. 3, error detection for another segment of the message segment), the second portion being less than all of the message to be checked for the one or more errors (Lin: paragraph 0050 & Fig. 3, divide message into a sequence of message segments); and
analyze the number of bits of the second portion of the message based on the error detection configuration (Lin: paragraph 0061 & Fig. 5A, bits of each message segment (i.e. message segment S+1)); and
the modification circuit is further configured to:
determine, based on analyzing of the first portion and the second portion, whether the message includes the one or more errors (Lin: paragraph 0051, generate error detection code for each segment).
Regarding Claim 14, Lin teaches the respective claim(s) as presented above and further teaches wherein:
the computation circuit is further configured to:
retrieve, from memory (Lin: paragraphs 0015-0016 memory), a first error detection value associated with analyzing the first portion of the message (Lin: paragraph 0061, error detection codes for message segments S); and
generate an aggregate error detection value of the message from the first error detection value and a second error detection value associated with analyzing the second portion of the message (Lin: paragraph 0051 & Fig. 3, said generating error detection code for each message segment of the sequence of message segments); and
the modification circuit is further configured to:
determine, based on the aggregate error detection value, whether the message includes the one or more errors (Lin: paragraphs 0051 & 0061, said error detection of each segment).
Regarding Claim 15, Lin teaches the respective claim(s) as presented above and further teaches wherein the modification circuit is further configured to:
identify an initial error detection value that was generated and edited into the message (Lin: paragraph 0051, parity codes may be generated for each message segment); and
determine whether the message includes the one or more errors by comparing the aggregate error detection value to the initial error detection value in the message (Lin: paragraphs 0051 & 0061, said error detection of each segment).
Regarding Claim 16, Lin teaches the respective claim(s) as presented above and further teaches wherein:
the error detection configuration is a first error detection configuration (Lin: paragraph 0051 & Fig. 3, parity codes (e.g., cyclic redundancy check (CRC) codes);
the number of bits is a first number of bits (Lin: paragraph 0061 & Fig. 5A, bits of first message segment S);
the computation circuit is further configured with a second error detection configuration of a plurality of error detection configurations (Lin: paragraph 0061, error detection codes for message segments S), the plurality of error detection configurations comprising the first error detection configuration and the second error detection configuration being different from the first error detection configuration (Lin: paragraph 0051 & Fig. 3, parity codes (e.g., cyclic redundancy check (CRC) codes) may be independently generated for each message segment independently of one another);
the computation circuit is further configured to:
identify, based on the second error detection configuration of the computation circuit, a third portion and a fourth portion of the message to be checked for the one or more errors (Lin: paragraphs 0050 & 0061, sequence of multiple segments (i.e. S+1, L, etc.)), the third portion and the fourth portion being less than all of the message to be checked for the one or more errors (Lin: paragraph 0050 & Fig. 3, divide message into a sequence of message segments);
analyze a second number of bits of the third portion and the fourth portion of the message based on the second error detection configuration (Lin: paragraph 0061 & Fig. 5A, bits of each message segment (i.e. message segment S, i.e. S+1, L, etc.)); and
the modification circuit is further configured to, based on analyzing the third portion and the fourth portion, determine whether the message includes the one or more errors (Lin: paragraph 0051, generate error detection code for each segment).
Regarding Claim 18, Lin teaches the respective claim(s) as presented above and further teaches wherein:
the error detection configuration is a first error detection configuration (Lin: paragraph 0051 & Fig. 3, said generating error detection code for each message segment of the sequence of message segments);
the message is a first message (Lin: paragraph 0050 & Fig. 3, message);
the number of bits is a first number of bits (Lin: paragraph 0061 & Fig. 5A, bits of first message segment S); and
the computation circuit is further configured with a second error detection configuration of a plurality of error detection configurations, the plurality of error detection configurations comprising the first error detection configuration and the second error detection configuration being different from the first error detection configuration (Lin: paragraph 0051 & Fig. 3, parity codes (e.g., cyclic redundancy check (CRC) codes) may be independently generated for each message segment independently of one another);
the computation circuit is further configured to:
identify, based on the second error detection configuration of the computation circuit, a third portion of a second message to be checked for the one or more errors (Lin: paragraphs 0050 & 0061, sequence of multiple segments (i.e. S+1, L, etc.)), the third portion being less than all of the second message to be checked for the one or more errors (Lin: paragraph 0050 & Fig. 3, divide message into a sequence of message segments);
analyze a second number of bits of the third portion of the second message based on the second error detection configuration (Lin: paragraph 0061 & Fig. 5A, bits of each message segment (i.e. message segment S, i.e. S+1, L, etc.)); and
the modification circuit is further configured to, based on analyzing the third portion, determine whether the second message includes the one or more errors (Lin: paragraph 0051, generate error detection code for each segment).
Regarding Claim 19, Lin teaches the respective claim(s) as presented above and further teaches wherein:
the computation circuit receives the third portion of the second message between the first portion of the first message and the second portion of the first message (Lin: paragraphs 0050 & 0061, sequence of multiple segments);
configuring of the computation circuit with the second error detection configuration is performed after analyzing the first portion of the message based on the first error detection configuration (Lin: paragraph 0051 & Fig. 3, said generating error detection code for each message segment of the sequence of message segments); and
the computation circuit is further configured with the first error detection configuration after analyzing the third portion of the second message based on the second error detection configuration (Lin: paragraph 0051 & Fig. 3, parity codes (e.g., cyclic redundancy check (CRC) codes) may be independently generated for each message segment independently of one another).
Regarding Claim 20, Lin teaches At least one computer-readable storage medium (Lin: paragraph 0078, computer readable medium comprising code executed on processor) having encoded thereon executable instructions that, when executed by at least one circuit (Lin: paragraphs 0050, 0071 & Figs. 3 & 7, apparatus (i.e. transmitter and/or receiver)), cause the at least one circuit to perform a method comprising:
identifying, based on an error detection configuration of the at least one circuit (Lin: paragraph 0051, error detection code), a first portion of the message (Lin: paragraph 0050 & Fig. 3, first segment of a sequence of multiple segments of a message) to be checked for errors (Lin: paragraph 0051, error detection code for each message segment) before a second portion of the message (Lin: paragraphs 0050-0051 & Fig. 3, another segment of the message segment) is available to the at least one circuit (Lin: paragraph 0064, progression indicator bit indicates that another segment exists after decoding first segment), the first portion being less than all of the message to be checked for one or more errors (Lin: paragraph 0050 & Fig. 3, divide message into a sequence of message segments);
analyzing a number of bits of the first portion of the message using the at least one circuit and based on the error detection configuration (Lin: paragraph 0061 & Fig. 5A, bits of each message segment (i.e. message segment S)); and
based on analyzing the first portion, determining whether the message includes the one or more errors (Lin: paragraph 0051, generate error detection code for each segment).
Response to Arguments
Applicants' arguments:
a) Lin alone or in combination fails to teach or suggest identifying a first portion of the message to be checked for errors before a second portion of the message is available to the circuit since the message of Lin is divided into message segments which are sent at the same time and there is no indication that any of the message segments are unavailable to the receiver when the receiver attempts to decode a first encoded message segment (remarks, page 14).
Applicant's arguments filed 04/03/2026 have been fully considered but they are not persuasive. After review of the prior art, Lin additional teaches a progression indicator bit may be included in each segment. For example, when receiver decodes the second message segment, (i.e. message segment S+1 in the message sequence), it also decodes another progression indicator bit which indicates to receiver that another segment exists (i.e. message segment L in the message sequence) (Lin: paragraph 0064). Examiner notes there would be no reason to provide said progression indicator bit to indicate another segment exists (after having decoded a previous segment) if the additional segment (i.e. segment L) was already known or available to the receiver. Since Lin teaches the receiver is made aware of additional segments that exist after having decoded a first segment in at least one embodiment, Lin similarly teaches decoding a first portion of a message before a second portion of a message is known or made available to a circuit.
Therefore the rejection of claims 1, 11 and 20 as being anticipated by Lin is maintained.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/NAJEEB ANSARI/Examiner, Art Unit 2463
/ASAD M NAWAZ/Supervisory Patent Examiner, Art Unit 2463
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